Self-Aligned Stacked Transistors with Direct Gate Coupling
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Solution Overview
Problem
Implementing 3D CMOS circuits with stacked transistors having different channel materials, such as non-silicon heterogeneous channel materials, poses challenges like misalignment and high costs due to sequential processing of PMOS and NMOS transistors, which complicates the integration and performance at low supply voltages.
Innovation Solution
The approach involves forming a channel stack with a first and second channel layer separated by a bonding layer, where both transistors are processed simultaneously using the same patterning steps, resulting in self-aligned transistors with direct gate-to-gate coupling, reducing the need for additional interconnects and minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If PMOS and NMOS transistors are processed sequentially with separate processing steps, then each transistor can be optimized for its specific channel material, but misalignment between transistors occurs and fabrication costs increase
Solution Approach 1:
The patent combines the processing of PMOS and NMOS transistors into a single concurrent processing step using a unified patterning approach. The method processes both transistor types simultaneously on the same substrate with shared processing steps, eliminating sequential processing while maintaining alignment through self-aligned fabrication techniques.
Solution Approach 2:
The patent employs a universal patterning method that can handle both PMOS and NMOS transistors with different channel materials using the same processing equipment and techniques. This multi-functional approach allows a single processing step to accommodate heterogeneous channel materials without requiring separate specialized processing lines.
2Ease of manufacture
If sequential processing is used for stacked transistors with different channel materials, then each transistor layer can be independently optimized, but fabrication costs and processing time increase
Solution Approach 1:
The patent merges multiple sequential processing operations into a single concurrent processing step. By processing both PMOS and NMOS transistor layers simultaneously using shared fabrication steps, the method reduces the total number of processing cycles required, thereby decreasing fabrication costs and improving manufacturing throughput.
Solution Approach 2:
The patent performs preliminary preparation of the substrate and channel material layers in advance, configuring the structure so that subsequent processing steps can handle both transistor types concurrently. This preliminary arrangement enables the unified patterning step to proceed efficiently without requiring separate processing sequences.
3Device complexity
If additional interconnects are added to couple gate electrodes in stacked transistors, then electrical connection is achieved, but device complexity and performance degradation increase
Solution Approach 1:
The patent extracts and eliminates the need for additional interconnect structures by implementing direct gate-to-gate coupling between stacked transistors. The method removes the intermediate interconnect layer that would otherwise be required, simplifying the device structure and reducing the number of fabrication steps needed for interconnect formation.
Solution Approach 2:
The patent employs asymmetric gate electrode design where the gate electrodes of stacked transistors are directly coupled through their inherent structural arrangement rather than through symmetric interconnect paths. This asymmetric coupling approach reduces the need for additional matching interconnect structures while maintaining electrical functionality.
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.