Stacked Transistors With Layered Active Regions for Threshold Control
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Solution Overview
Problem
Conventional methods face difficulties in forming transistors with different threshold voltages in a stacked integrated circuit device, particularly due to the overlap of upper transistors on lower transistors, which complicates the formation of gate electrode layers.
Innovation Solution
The integrated circuit devices incorporate a stacked structure with upper and lower transistors having different active region materials, allowing for the formation of transistors with varying threshold voltages without multiple patterning of gate electrode layers, achieved through the use of an inner and outer semiconductor layer combination in the upper active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple stacked transistors having different threshold voltages are included in a device to reduce leakage power, then power efficiency is improved, but it becomes difficult to form transistors having different threshold voltages using conventional methods due to upper transistors overlapping lower transistors
Solution Approach 1:
The upper active region is segmented into an inner layer and an outer layer with different semiconductor materials. This segmentation allows different threshold voltages to be achieved in different regions of the upper transistor, enabling multiple threshold voltage characteristics within a single stacked transistor structure without requiring multiple patterning steps.
Solution Approach 2:
Different semiconductor materials are used in the inner layer and outer layer of the upper active region to create local variations in threshold voltage. The inner layer can have one material composition while the outer layer has a different material composition, allowing localized control of electrical properties to achieve different threshold voltages in different regions.
2Ease of manufacture
If conventional methods are used to form gate electrode layers in stacked transistors, then manufacturing process is simplified, but it becomes difficult to achieve different threshold voltages in upper and lower transistors
Solution Approach 1:
The threshold voltage is controlled by changing the material composition parameter in the active region. By varying the semiconductor material in the inner and outer layers of the upper active region, different threshold voltages can be achieved without changing the gate electrode layer formation process, thus maintaining manufacturing simplicity while achieving threshold voltage variation.
3Area of stationary object
If stacked transistor structure is used to reduce device area, then area requirements are reduced to close to one-half of non-stacked devices, but complexity in forming transistors with different threshold voltages increases
Solution Approach 1:
The active region is extended into the vertical dimension with an inner layer and outer layer structure. This vertical dimensionality allows different materials to be stacked in the thickness direction, enabling different threshold voltages to be achieved within the same planar footprint, thus maintaining area reduction while managing complexity through vertical material variation.
Data Source
AI summary
Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.