Stacked Nanostructure Transistors With Epitaxial Leakage Isolation

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Solution Overview

Problem

Current semiconductor integrated circuit (IC) manufacturing faces challenges in reducing current leakage in source/drain epitaxial structures, which affects the performance and efficiency of ICs as they scale down in size and complexity.

Innovation Solution

The implementation of an epitaxial stack with an isolation structure between source/drain epitaxial structures, utilizing epitaxial layers with different compositions and thicknesses to form diodes that suppress junction current, thereby reducing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If source/drain epitaxial structures are scaled down to increase functional density, then IC production efficiency and cost are improved, but current leakage increases and device performance deteriorates

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcurrent leakage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An epitaxial isolation structure composed of alternating n-type and p-type semiconductor layers is introduced between the source/drain epitaxial structures. This intermediary structure forms diode junctions that actively suppress leakage current, allowing continued scaling while maintaining device performance and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The isolation structure utilizes changes in material composition and doping parameters, alternating between n-type and p-type semiconductor layers with specific thicknesses. These parameter variations create diode junctions that selectively block leakage current while maintaining compatibility with scaled device dimensions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If epitaxial isolation structures are added between source/drain structures, then current leakage is reduced and device performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecurrent leakage suppressionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The alternating n-type and p-type semiconductor layers are formed epitaxially in advance, creating the isolation structure and diode junctions before final device assembly. This preliminary formation integrates the isolation function into the existing epitaxial growth process, reducing the need for additional complex manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The epitaxial layers serve multiple functions: they act as both the isolation structure between source/drain regions and as active diode junctions for leakage suppression. This multi-functionality consolidates what could be separate structures into a single integrated solution, simplifying the overall device architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively isolates source/drain epitaxial structures, enhancing carrier mobility and device performance by reducing current leakage and allowing for the vertical stacking of transistors, which can lead to smaller and more efficient ICs.

Implementation Method 1

an epitaxial isolation structure between source/drain epitaxial structures

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS12170227B2Stacked semiconductor device with nanostructure channels
Publication Date: 2024.12.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12170227B2 patent drawing
  • US12170227B2 patent drawing
  • US12170227B2 patent drawing

AI summary

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.