Stacked Nanostructure Transistors for One-Transistor Logic Footprints
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Solution Overview
Problem
As semiconductor devices continue to shrink in size to increase integration density, challenges arise in maintaining effective manufacturing processes and device performance, particularly in forming efficient and densely packed transistors.
Innovation Solution
The development of stacked transistors with multiple vertically stacked nanostructure-FETs, including lower and upper gate structures, allows for the formation of logic devices with a small footprint by using separate control for lower and upper semiconductor nanostructures, enabling efficient interconnection and high device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing process effectiveness and device performance deteriorate
Solution Approach 1:
The patent transitions from planar transistor arrangements to three-dimensional stacked transistor structures. Multiple transistor channels are stacked vertically to form a column, enabling more transistors to be packed into a smaller footprint area. This vertical stacking approach moves the integration density improvement from the two-dimensional plane to the three-dimensional space, effectively resolving the contradiction between increasing component quantity and maintaining manufacturing precision.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device performance deteriorates
Solution Approach 1:
By stacking transistor channels vertically, the invention achieves higher integration density without compromising individual transistor performance. The vertical stacking allows each transistor in the stack to maintain its functional integrity while contributing to the overall increased component density.
Solution Approach 2:
The stacked transistor structure divides the transistor channel into multiple segments stacked vertically. Each segment (individual transistor channel) can be independently controlled by its own gate, allowing for optimized performance of each segment while achieving high overall integration density. The segmentation enables separate control of lower and upper semiconductor nanostructures.
3Area of stationary object
If stacked transistor structure is used to achieve small footprint, then integration density improves, but device complexity increases
Solution Approach 1:
The patent employs vertical stacking to reduce the horizontal footprint of transistor structures. By arranging multiple transistor channels in the vertical dimension rather than spreading them out in the horizontal plane, the invention achieves compact device layouts with smaller footprints while the modular stacked architecture helps manage structural complexity.
Solution Approach 2:
The stacked transistor structure serves multiple functions: it increases integration density, reduces footprint area, and enables series or parallel connections of nanostructure-FETs for enhanced performance. The common source and drain regions in the stacked structure provide shared electrical connections, reducing the need for separate interconnect structures and thereby managing complexity.
Data Source
AI summary
Various embodiments include stacked transistors and methods of forming stacked transistors. In an embodiment, a device includes: a first nanostructure; a second nanostructure above the first nanostructure; a first gate structure extending along a top surface and a bottom surface of the first nanostructure; and a second gate structure extending along a top surface and a bottom surface of the second nanostructure. The first gate structure is disposed at a first side of the first nanostructure and a first side of the second nanostructure. The second gate structure is disposed at a second side of the first nanostructure and a second side of the second nanostructure. The second side of the first nanostructure is opposite the first side of the first nanostructure. The second side of the second nanostructure opposite the first side of the second nanostructure.