Stacked Transistors Sharing Metal Gate for FinFET Integration

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Solution Overview

Problem

Conventional FinFET fabrication faces challenges in integrating a metal gate and contact plugs, particularly in scaling down to 65 nm and below, which affects the performance and structure of semiconductor devices.

Innovation Solution

A semiconductor device and method where two transistors share a common metal gate structure, with a channel layer and source/drain overlapping the first transistor's metal gate structure, enabling better integration and performance by forming a second transistor on top of the first, sharing the same metal gate structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional FinFET fabrication is used to scale down to 65 nm and below, then transistor size is reduced, but integration of metal gate and contact plugs becomes difficult

Engineering Contradiction:

Improvetransistor sizeVSAvoidintegration of metal gate and contact plugs

Core Design Contradiction:

Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent transitions from planar transistor layout to three-dimensional stacked transistor architecture, where transistors are arranged vertically rather than horizontally. This dimensional change allows continued scaling at 65 nm and below while maintaining manufacturability, as the vertical stacking enables metal gate and contact plug integration in the third dimension rather than competing for planar space

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested transistor structures where one transistor is positioned above another, sharing common components such as the gate electrode and channel region. This nesting approach allows compact integration of multiple transistors in a vertical stack, resolving the manufacturing difficulty of integrating metal gates and contact plugs at scaled dimensions

Inventive Principle:

Principle #7Nested doll (Nesting)

2Ease of manufacture

If planar MOS transistor structure is used, then fabrication is simpler, but channel control is insufficient leading to DIBL and short channel effects

Engineering Contradiction:

Improvefabrication simplicityVSAvoidchannel control

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent employs a three-dimensional FinFET structure with vertical fins extending from the substrate, transforming the traditional planar channel into a vertically-oriented channel region. This dimensional change provides superior gate control over the channel while maintaining compatibility with standard fabrication processes, effectively reducing DIBL and short channel effects without sacrificing manufacturability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10068919B2Semiconductor device and method of forming the same

Publication Date: 2018.09.04 UNITED MICROELECTRONICS CORP

AI summary

A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.