Stacked Transistors with Variable Channel Widths
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Solution Overview
Problem
Conventional integrated circuit devices face limitations in optimizing transistor performance due to fixed channel widths across different strata, leading to performance tradeoffs between PMOS and NMOS transistors.
Innovation Solution
The integration of stacked transistors with strata having channel materials of different widths, allowing for tailored geometry and material configurations such as fin-shaped silicon/germanium and wire-shaped III-V materials, enabling independent optimization of transistor dimensions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed channel widths are used across different strata, then manufacturing simplicity is maintained, but transistor performance optimization is limited
Solution Approach 1:
The patent implements different channel widths for different strata (first stratum with first channel width, second stratum with second channel width) to optimize performance for specific transistor types such as PMOS and NMOS transistors, allowing each stratum to have locally optimized characteristics rather than a uniform global configuration
Solution Approach 2:
The device is segmented into multiple strata with independently optimized channel widths, where the first stratum and second stratum can have different channel width configurations tailored to their specific functional requirements, enabling independent optimization of each segment
2Reliability
If uniform channel widths are used for all transistors, then device simplicity is maintained, but carrier transport optimization is hindered
Solution Approach 1:
Different channel widths are assigned to different strata to locally optimize carrier transport characteristics, with the first stratum configured for one transistor type and the second stratum configured for another transistor type, allowing each region to have optimal geometry for its specific function
3Reliability
If same channel width is used across strata, then manufacturing precision requirements are simplified, but off-state leakage reduction is limited
Solution Approach 1:
The patent applies different channel widths to different strata to locally optimize off-state leakage characteristics for specific transistor types, allowing each stratum to have geometry optimized for minimizing leakage in that particular region rather than using a single width for all transistors
Data Source
AI summary
Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.