Stacked Deep Trench Capacitors for Higher Capacitance Density
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Solution Overview
Problem
Conventional planar capacitors face challenges in increasing capacitance without occupying excessive space, which affects miniaturization and complicates through silicon via formation due to increased depth and area requirements.
Innovation Solution
A stacked semiconductor structure with deep trench capacitors on multiple substrates, connected via hybrid bond or conductive bumps, allowing for increased capacitance without altering the size or height of individual capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the capacitor is increased to store more charges, then the capacitance is improved, but the occupied area of the semiconductor device increases
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by stacking multiple substrates vertically. This dimensional change allows capacitance to be increased through the vertical stacking of multiple capacitors rather than expanding the horizontal area of a single capacitor, thereby resolving the contradiction between charge storage capacity and occupied area.
Solution Approach 2:
The patent divides a single large capacitor into multiple smaller capacitors distributed across several stacked substrates. Each substrate contains multiple deep trench capacitors, and the substrates are stacked vertically with electrical connections between corresponding capacitors on adjacent substrates. This segmentation allows the total capacitance to be increased while maintaining a compact footprint area.
2Quantity of substance
If the area of the capacitor is increased to store more charges, then the capacitance is improved, but the through silicon via formation becomes difficult due to increased depth requirements
Solution Approach 1:
The patent segments the through-silicon-via formation process into multiple shorter via formations across different substrates in the stack. Instead of forming one deep via through a single thick substrate, multiple shallower vias are formed through individual thinner substrates that are then stacked. This segmentation makes via formation easier and more manufacturable while achieving the same total capacitance.
Solution Approach 2:
The patent moves the capacitance accumulation from the horizontal plane to the vertical stacking dimension. By forming multiple capacitors on separate substrates and stacking them, the effective capacitance area is increased without requiring deeper individual substrates or more complex via structures, thereby simplifying manufacturing.
3Quantity of substance
If the height of the capacitor is increased to store more charges, then the capacitance is improved, but the occupied area affects other devices
Solution Approach 1:
The patent resolves this contradiction by shifting the capacitance expansion from the horizontal area dimension to the vertical stacking dimension. Multiple substrates with deep trench capacitors are stacked vertically, allowing the total capacitance to be doubled or tripled without increasing the footprint area, thus preventing interference with other devices on the same chip.
Data Source
AI summary
The invention provides a semiconductor structure, which comprises a first substrate and a second substrate stacked with each other. A first passive element is located in the first substrate and a second passive element is located in the second substrate. A first wire layer is located on a top surface of the first substrate and electrically connected with the first passive element, and a conductive pad is located on a bottom surface of the second substrate and directly contacts the first wire layer.