Embedded Stacked Trench Capacitors for Compact High-Capacitance Packages
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Solution Overview
Problem
There is a need for packages with improved performance and reduced size that incorporate substrates and integrated devices, where existing technologies struggle to achieve high capacitance density while maintaining compact form factors.
Innovation Solution
The use of stacked trench capacitor devices within the substrate, which include a core layer with interconnects, dielectric layers, and vertically stacked trench capacitor devices, allowing for high capacitance density and reduced package inductance, enabling more compact designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor designs are used, then package size is reduced, but capacitance density is insufficient
Solution Approach 1:
The patent implements stacked trench capacitor devices that extend vertically through multiple layers of the substrate, transitioning from planar to three-dimensional capacitor structures. This vertical stacking approach increases capacitance density by utilizing the third dimension (height) rather than only horizontal space, thereby achieving higher capacitance without proportionally increasing package footprint.
Solution Approach 2:
The trench capacitor devices are embedded within the substrate core layer, with capacitor structures nested inside trenches formed in the substrate. This nesting approach allows capacitor elements to be integrated within the existing substrate structure rather than adding external components, maximizing space utilization and increasing capacitance density within the same volume.
2Quantity of substance
If more capacitor elements are added to increase capacitance density, then package complexity increases
Solution Approach 1:
The patent combines multiple capacitor elements into integrated stacked trench capacitor devices that are formed as unified structures within the substrate. Rather than adding discrete capacitor components, the design merges capacitor functionality into the substrate itself through integrated trench structures, dielectric layers, and conductive elements, thereby increasing capacitance density while minimizing the increase in overall package complexity.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, contains interconnect structures for signal routing, and houses the stacked trench capacitor devices for energy storage. This multi-functionality allows the same substrate structure to fulfill both interconnection and capacitance requirements, reducing the need for separate dedicated capacitor components and thereby limiting the increase in package complexity.
3Volume of moving object
If compact designs are implemented, then package size is reduced, but performance is compromised
Solution Approach 1:
The patent changes the geometric parameters of capacitor structures by implementing vertical stacking with increased height-to-footprint ratio. The stacked trench capacitors utilize greater vertical extent (z-dimension) while maintaining compact horizontal dimensions, thereby achieving high capacitance density in a small footprint without compromising performance. The dielectric layer thickness and trench dimensions are optimized to maintain electrical performance while minimizing overall package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides packages with enhanced performance and reduced size by achieving high capacitance density and compact form factors, enabling better utilization of space within the package.
Implementation Method 1
The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer
Data Source
AI summary
A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.