Stacked Trench Contacts and Gate Straps for FinFET Alignment
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Solution Overview
Problem
The challenge of controlling overlay misalignment between electrically conductive structures in transistor arrangements, such as trench contacts and metal gates, becomes increasingly difficult as transistor dimensions shrink, leading to issues with edge placement error margins and high gate resistance, which conventional fabrication processes struggle to address efficiently.
Innovation Solution
Transistor arrangements with stacked trench contacts and gate straps are introduced, where a first trench contact is formed over a S/D contact, recessed, and a second trench contact is formed over the first, with a gate contact being self-aligned and electrically isolated, reducing gate resistance and improving edge placement error margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used, then manufacturing is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and device density while maintaining manufacturability through established semiconductor processing techniques adapted for vertical geometries.
Solution Approach 2:
The patent implements stacked transistor arrangements where multiple FinFET devices are vertically stacked and interconnected through shared components. Transistors are nested within each other vertically, with drain contacts and interconnect structures serving multiple stacked devices, thereby increasing device density without proportionally increasing manufacturing complexity.
2Productivity
If transistor size is reduced to increase density, then device density improves, but manufacturing precision requirements increase
Solution Approach 1:
Instead of reducing lateral dimensions only, the patent extends transistor structures vertically into the third dimension with fins having heights significantly greater than their lateral widths. This allows device scaling while maintaining larger lateral dimensions that are easier to manufacture with existing precision capabilities.
Solution Approach 2:
The transistor channel is segmented into vertical fin structures rather than a continuous planar layer. This segmentation allows the channel to be formed through self-aligned processes where the fin sidewalls define subsequent layer patterns, reducing the need for ultra-precise lithographic alignment at each step.
3Productivity
If more interconnect layers are added to support higher density, then device density improves, but manufacturing complexity increases
Solution Approach 1:
Drain contacts for stacked transistors are formed as shared structures that serve multiple devices vertically. A single drain contact region underlying a stack of fins provides electrical connection to all fins in the stack through the shared drain region, eliminating the need for separate drain contacts for each transistor in the stack.
Solution Approach 2:
The shared drain contact structure performs multiple functions: it serves as the drain electrode for multiple stacked transistors, provides a common electrical connection point, and acts as an interconnect element. This multi-functionality reduces the total number of interconnect layers and manufacturing steps required.
Data Source
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AI summary
Disclosed herein are transistor arrangements with trench contacts that have two parts - a first trench contact and a second trench contact - stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.