Stacked Trench Contacts and Gate Contacts Without Caps
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to control the overlay between electrically conductive structures of trench contacts and metal gates, and between trench contacts and adjacent gate contacts with high precision, especially as transistor dimensions decrease, while also addressing issues of gate resistance and cost-efficiency in fabrication processes.
Innovation Solution
The implementation of stacked trench contacts (TCN1 and TCN2) and gate contacts without gate caps, where TCN1 is self-aligned using a thin temporary cap, and TCN2 has an inverse taper shape with a higher dielectric constant spacer, allowing for improved edge placement error margin and reduced probability of shorts and dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional trench contact alignment methods are used, then manufacturing process is simpler, but overlay precision between trench contacts and metal gates deteriorates
Solution Approach 1:
The patent applies preliminary action by forming a temporary gate cap structure before trench contact formation. This temporary structure pre-establishes the alignment reference that will be used throughout subsequent processing steps, ensuring precise overlay between trench contacts and metal gates while maintaining a manageable fabrication process
Solution Approach 2:
The patent uses an intermediary approach by introducing a temporary gate cap as a mediating structure. This temporary cap serves as an alignment intermediary that facilitates precise positioning of trench contacts relative to metal gates, and is later removed after serving its alignment purpose
2Productivity
If transistor dimensions are reduced to increase density, then productivity increases, but overlay control precision deteriorates
Solution Approach 1:
By pre-forming the temporary gate cap structure before trench contact formation, the patent establishes an alignment reference that remains effective even as transistor dimensions are reduced. This preliminary structure enables maintained overlay precision despite increased transistor density requirements
Solution Approach 2:
The patent addresses dimension scaling by changing the approach to alignment rather than relying on direct geometric scaling. The temporary gate cap provides a parameter-based alignment solution that remains effective across different transistor size regimes, enabling high density while maintaining precision
3Manufacturing precision
If gate caps are used for alignment, then overlay precision improves, but probability of dielectric breakdown and shorts increases
Solution Approach 1:
The temporary gate cap is formed preliminarily for alignment purposes only. After serving its alignment function during trench contact formation, it is removed before final device operation. This preliminary use eliminates the reliability issues of permanent gate caps while maintaining their alignment benefits
Solution Approach 2:
The patent extracts the alignment function from the permanent gate structure by using a temporary gate cap that is removed after alignment. This separation takes out the harmful presence of a permanent cap that could cause dielectric breakdown, while retaining the useful alignment function during critical fabrication steps
4Device complexity
If conventional single-level trench contacts are used, then device complexity is lower, but capacitance between adjacent gates increases
Solution Approach 1:
The patent segments the trench contact structure into multiple levels (first and second trench contacts at different depths). This segmentation allows the contact structure to pass between adjacent gates at different vertical positions, reducing capacitive coupling between gates while maintaining a relatively simple overall contact architecture
Data Source
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AI summary
Described herein are fabrication processes and resulting transistor arrangements with trench contacts that have two parts - a first trench contact (TCN1) and a second trench contact (TCN2) - stacked over one another, and with gate contacts (VCGs). In such transistor arrangements, the TCN1 may be self-aligned to adjacent gates and may be used to make cell-level connections, the TCN2 may also make cell-level connections and may be provided after the self-aligned TCN1 formation and may have an inverse taper shape, the spacer around the TCN2 may be a higher dielectric constant dielectric material than conventional spacer materials, and the VCGs may be formed without the presence of any gate caps or after using only thin temporary gate caps. Fabrication processes and transistor arrangement described herein may provide several improvements in terms of increased edge placement error margin, cost-efficiency, and device performance.