Stacked Trigate Transistors with Sub-30 Nm Dielectric Isolation
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Solution Overview
Problem
Conventional methods fail to achieve sub-30 nm dielectric isolation between top and bottom fin channels in stacked tri-gate transistors, limiting performance as transistors are scaled to smaller sizes.
Innovation Solution
A thin dielectric layer, such as SiO2, SiON, SiCN, or HfO2, is used to isolate the fin channels in vertically stacked FinFET transistors, enabling area scaling and improved performance without the need for layer transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bonding is used to create dielectric isolation between top and bottom fin channels, then the isolation structure can be formed, but sub-30 nm dielectric isolation thickness is not achievable
Solution Approach 1:
The patent divides the isolation formation process into multiple stages: first forming a preliminary isolation layer, then performing selective etching to create recesses, and finally depositing additional dielectric material to achieve the target sub-30 nm thickness. This segmented approach enables precise thickness control that cannot be achieved through single-step bonding methods.
Solution Approach 2:
The patent performs preliminary actions by first depositing a thicker dielectric layer that exceeds the final required thickness, then selectively removing material through etching processes. This preliminary over-deposition followed by selective removal allows for precise achievement of sub-30 nm isolation thickness with better control compared to direct thin-film deposition.
2Productivity
If dielectric isolation thickness is reduced to improve transistor scaling, then performance is improved, but conventional bonding approaches cannot achieve sub-30 nm thickness
Solution Approach 1:
The patent replaces mechanical bonding approaches with a combination of chemical vapor deposition (CVD) and plasma etching processes. This substitution of mechanical systems with chemical and plasma-based processes enables atomic-level precision in thickness control, achieving sub-30 nm isolation that mechanical bonding cannot attain.
Solution Approach 2:
The patent utilizes parameter changes in the dielectric deposition and etching processes, including controlling deposition temperature, pressure, and gas flow rates, as well as adjusting etching power and chemistry. These parameter optimizations enable precise control of the final isolation thickness at sub-30 nm scales while maintaining manufacturing feasibility.
Data Source
AI summary
A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.