Stacked TSV Semiconductor Package for Lower Voltage Drop
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, high performance, and high capacitance while maintaining improved voltage characteristics.
Innovation Solution
The semiconductor package design involves stacking semiconductor chips with through-silicon vias (TSV) in a vertical direction, utilizing multiple semiconductor chips with specific integrated circuits, through-electrodes, and sealing layers to enhance electrical connections and voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked in a vertical direction to achieve miniaturization, then the package size is reduced, but voltage characteristics deteriorate due to increased resistance and voltage drop
Solution Approach 1:
The patent applies local quality by differentiating the pad structures into two groups: first group pads with smaller via diameters for signal transmission, and second group pads with larger via diameters for power supply. This localized differentiation optimizes each region's function - signal pads maintain integrity while power pads minimize resistance and voltage drop, resolving the contradiction between miniaturization and voltage characteristics.
Solution Approach 2:
The patent segments the rear pads into two distinct groups with different via configurations. The first group of rear pads connects to first through-vias with a first diameter, while the second group of rear pads connects to second through-vias with a second diameter larger than the first. This segmentation allows independent optimization of power and signal pathways within the compact stacked package.
2Reliability
If through-vias with larger diameter are used to reduce resistance, then voltage characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by assigning different via diameter specifications to different pad groups. Second group pads (power pads) use larger via diameters to reduce resistance, while first group pads (signal pads) use smaller via diameters. This localized approach concentrates the manufacturing precision requirements only where larger vias are needed for power delivery, rather than requiring all vias to meet high precision standards.
3Reliability
If multiple through-vias are used to improve voltage characteristics, then electrical connection reliability improves, but device complexity increases
Solution Approach 1:
The patent segments the electrical connection pathways into two distinct systems: one system using first through-vias for signal transmission and another system using second through-vias for power supply. This segmentation organizes the complexity into manageable, functionally-separated groups, making the multi-via structure more systematic and easier to manufacture despite the increased number of connections.
Solution Approach 2:
The patent resolves complexity by transitioning from planar to three-dimensional stacking architecture. Multiple chips are stacked vertically with through-vias penetrating each chip layer, utilizing the vertical dimension to achieve high electrical connection reliability without increasing the horizontal footprint or lateral complexity of the package structure.
Data Source
AI summary
Provided is a semiconductor package, including a first semiconductor chip including a plurality of first through-electrodes, a second semiconductor chip including a plurality of second through-electrodes, at least one third semiconductor chip including a plurality of third through-electrodes, a plurality of first through-vias electrically connected to a second group of first rear pads, a plurality of second through-vias electrically connected to the plurality of first through-vias, and tapered toward the plurality of first through-vias, and a plurality of connection bumps electrically connected to the plurality of third rear pads and the plurality of second through-vias, wherein a maximum diameter of the plurality of second through-vias is larger than a maximum diameter of the plurality of first through-vias in a horizontal direction.