Stacked TVS Die Layout for High-Current ESD Protection
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Solution Overview
Problem
Semiconductor devices are vulnerable to damage from electrostatic discharge (ESD), electrical overstress (EOS), and electrical fast transients (EFT), and existing protection methods often require larger package sizes to handle increased current, which contradicts the goal of miniaturization in semiconductor manufacturing.
Innovation Solution
The solution involves stacking semiconductor die with protection circuits in a small package form-factor, where multiple discrete transient voltage suppression (TVS) diodes are connected in parallel, using conductive through-silicon vias (TSVs) and bumps to distribute high ESD current across multiple die, thereby increasing protection capability without enlarging the package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor package size is increased to include more die area for handling higher electric current, then the ESD protection capability is improved, but the package size becomes larger which contradicts the goal of miniaturization
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of protection circuits to a three-dimensional stacked configuration using through-silicon vias (TSVs). Multiple TVS diode arrays are stacked vertically, allowing the system to increase the total silicon surface area for ESD discharge without increasing the package footprint. This vertical stacking enables higher ESD protection capability while maintaining a compact package size.
Solution Approach 2:
The patent implements a nested structure where multiple TVS diode arrays are stacked within the same package footprint. Each layer of TVS diodes is nested within the vertical space defined by TSVs, creating a compact three-dimensional arrangement. This nesting allows multiple protection circuits to coexist in a small package volume, simultaneously achieving high ESD protection and miniaturization.
2Reliability
If multiple TVS diode arrays are stacked to increase silicon surface area for ESD discharge, then the ESD protection capability is enhanced, but the device complexity increases due to additional interconnection structures
Solution Approach 1:
The patent divides the ESD protection function into multiple segmented TVS diode arrays stacked in separate layers. Each layer contains discrete TVS diodes that can be independently formed and connected. This segmentation allows the complex ESD protection function to be distributed across multiple simpler units, making the overall system more manageable despite the increased number of components.
Solution Approach 2:
The through-silicon vias (TSVs) serve multiple functions simultaneously: they provide mechanical support for stacking, enable electrical interconnection between layers, and facilitate heat dissipation. This multi-functionality reduces the need for additional specialized structures, thereby limiting the increase in device complexity despite the stacked configuration.
3Reliability
If the protection circuit is designed to handle higher electric current, then the ESD protection capability is improved, but the power consumption increases during normal operation
Solution Approach 1:
The patent employs TVS diodes that dynamically switch between high-impedance and low-impedance states based on voltage conditions. During normal operation, the TVS diodes maintain a high-impedance state that minimizes power consumption. When an ESD event occurs and voltage exceeds the breakdown threshold, the diodes transition to a low-impedance state to conduct high current. This dynamic behavior allows the protection circuit to provide high ESD protection capability while consuming minimal power during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ESD protection capability significantly by distributing high ESD currents through multiple parallel protection circuits, maintaining a small package size and increasing the silicon surface area for discharge, effectively isolating semiconductor packages from ESD events.
Implementation Method 1
using conductive through-silicon vias (TSVs) and bumps to distribute high ESD current across multiple die
Implementation Method 2
multiple discrete transient voltage suppression (TVS) diodes are connected in parallel
Data Source
Figure 1
Figure 2a~2c
Figure 2d~3
AI summary
A semiconductor device having a first semiconductor die (124c,170,198,124b) with a protection circuit (150) and a second semiconductor die (124b, 124,206,124a) with a protection circuit (150) is disposed over the first semiconductor die; where the protection circuits on each semiconductor die are coupled in parallel. The die are stacked and electrically connected in parallel between leadframe (160) first terminal(160a) and second terminal (160b) through an interconnect structure (134a,140a,140b). An encapsulant (162) is deposited around the first semiconductor die, second semiconductor die, and leadframe. Electrical current from an ESD event is routed through each semiconductor die in parallel to a ground voltage node and the semiconductor packages are thus isolated from an ESD event. At least two semiconductor die with protection circuits may be stacked to increase the ESD current discharge capability.