Stacked Variable Resistance Memory Block for Data Processing
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Solution Overview
Problem
Current semiconductor data processing systems face challenges in integrating different memory types with varying driving conditions, leading to increased complexity and cost due to the need for separate driving circuits, and trade-offs between speed, capacity, and power consumption in DRAM and flash memory devices.
Innovation Solution
A data processing system is designed with a combined memory block comprising stacked layers of variable resistance memory cells, where a working memory and storage memory are allocated to different layers, allowing for efficient data processing and storage with improved integration density and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate memory chips (DRAM and flash) are integrated in an SOC data processing system, then functional versatility is improved, but device complexity increases due to separate driving circuits being required for each memory type
Solution Approach 1:
The patent combines DRAM and flash memory onto a single memory chip, eliminating the need for separate driving circuits for each memory type. This merging approach maintains functional versatility while reducing overall device complexity by sharing common driving circuitry between the two memory types.
Solution Approach 2:
The memory chip is designed to perform multiple functions by integrating both DRAM and flash memory on the same substrate, allowing a single chip to serve as both working memory and storage memory, thereby reducing the need for separate specialized circuits for each function.
2Speed
If DRAM is used for working memory, then operational speed is improved, but power consumption increases due to refresh operations and larger capacitor requirements
Solution Approach 1:
The patent combines DRAM and flash memory on a single chip, allowing the system to leverage DRAM's speed for active operations while using flash for storage, thereby optimizing the balance between speed and power consumption by strategically placing data in the appropriate memory type.
3Quantity of substance
If flash memory is used for storage, then integration density is improved, but operation voltage increases due to stack structure requiring higher voltages
Solution Approach 1:
The patent integrates DRAM and flash memory on a single chip with shared driving circuits, allowing the system to optimize voltage usage by directing low-voltage operations to DRAM and high-voltage operations to flash memory only when necessary, thereby managing power consumption more effectively.
4Ease of manufacture
If separate memory chips are mounted in an SOC system, then manufacturing flexibility is improved, but manufacturing cost increases due to increased process complexity
Solution Approach 1:
The patent combines DRAM and flash memory onto a single memory chip that can be mounted as one component in the SOC system. This approach maintains manufacturing flexibility while reducing manufacturing process complexity by eliminating the need for separate mounting and wiring processes for individual memory chips.
Data Source
AI summary
A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.