Stacked Varistor Electrode Layout for Stable Capacitance Matching
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Solution Overview
Problem
Conventional varistors generate stray capacitance between internal and external electrodes, leading to variations in electrostatic capacitance, especially when used in pairs, which affects the performance of miniaturized electronic devices.
Innovation Solution
A stacked varistor configuration with specific electrode arrangements and projections is used, where internal electrodes are strategically positioned to overlap and extend beyond external electrodes, reducing stray capacitance variations by ensuring consistent electrostatic capacitance between pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional varistor configuration is used, then varistor voltage can be secured, but stray capacitance varies due to external electrode variations
Solution Approach 1:
The patent applies preliminary action by extending the internal electrodes beyond the external electrodes before the final product assembly. This pre-positioning of internal electrodes protruding from the sintered body ensures that even if external electrodes vary in position or shape, the critical varistor regions maintain consistent spacing and alignment, thereby reducing stray capacitance variations while preserving varistor voltage characteristics
Solution Approach 2:
The patent applies local quality by creating distinct regions with different functional characteristics. The internal electrodes are designed to extend beyond external electrodes in specific locations, creating localized protruding regions that compensate for external electrode variations. This localized structural modification ensures consistent electrostatic capacitance in critical areas without affecting the overall varistor voltage performance
2Volume of moving object
If varistors are miniaturized for electronic devices, then device size is reduced, but electrostatic capacitance control becomes more difficult
Solution Approach 1:
The patent applies dimensionality change by extending internal electrodes in the direction perpendicular to the sintered body surface, creating a three-dimensional electrode configuration. This vertical extension beyond the external electrodes provides an additional degree of freedom for controlling electrostatic capacitance, allowing miniaturization while maintaining consistent capacitance values through precise control of electrode protrusion depth and position
3Measurement precision
If two varistors are formed in one element to reduce capacitance difference, then pairing precision is improved, but stray capacitance variation increases
Solution Approach 1:
The patent applies preliminary action by pre-positioning internal electrodes to extend beyond external electrodes in a standardized configuration. This pre-established geometric relationship ensures that when multiple varistors are formed in one element, the critical dimensions are controlled from the outset, reducing both capacitance matching errors and stray capacitance variations through consistent electrode alignment and spacing
Solution Approach 2:
The patent applies parameter changes by modifying the geometric parameters of internal electrodes, specifically their extension length and position relative to external electrodes. By controlling these parameters, the patent optimizes the balance between stray capacitance reduction and electrostatic capacitance consistency, enabling improved pairing precision without excessive stray capacitance variation
Data Source
AI summary
A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.