Stacked Vertical FETs With Self-Aligned Junctions
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Solution Overview
Problem
The challenge in scaling complementary metal-oxide semiconductors (CMOS) beyond the 5 nanometer node lies in effectively stacking planar field-effect transistors (FETs), which is complicated by their horizontal orientation, whereas vertical FETs offer a promising alternative but require innovative techniques for stacking.
Innovation Solution
A method for forming stacked vertical field-effect transistors (VFETs) involves creating a trench in a semiconductor substrate with a sequence of dielectric layers, growing a fin epitaxially within the trench, and using sacrificial layers to separate and isolate bottom and top VFET devices, allowing for the deposition of oxide materials and metal gates, thereby facilitating vertical stacking and area scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If planar FETs are stacked vertically, then CMOS area scaling is achieved, but the stacking process becomes extremely challenging due to horizontal orientation
Solution Approach 1:
The patent inverts the conventional horizontal planar FET architecture into a vertical orientation. The channel is formed vertically along the sidewalls of a sacrificial mandrel, with source and drain regions positioned at the top and bottom ends of the channel, respectively. This inversion enables vertical stacking of multiple FETs while maintaining proper device functionality and significantly improving area scaling efficiency.
Solution Approach 2:
The patent transitions from two-dimensional planar FETs to three-dimensional vertically stacked FETs. By utilizing the vertical dimension for stacking multiple FETs along the sidewalls of a common sacrificial structure, the design achieves higher device density without increasing the planar footprint, effectively adding a third dimension to the device architecture.
2Ease of manufacture
If vertical FETs are designed with unique structure, then stacking is facilitated, but device complexity increases
Solution Approach 1:
The patent segments the vertical channel into multiple discrete FET devices by positioning different gate structures at different heights along the channel. Each FET is defined by its own gate electrode and associated source-drain regions, allowing independent control while sharing common structural elements like the sacrificial mandrel and substrate interface.
Solution Approach 2:
The sacrificial mandrel structure serves multiple functions: it defines the channel geometry, provides a template for vertical epitaxial growth, and acts as a common support structure for stacked FETs. The gate dielectric and gate electrode structures also serve dual purposes by providing both electrical control and structural definition for multiple FET devices simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient vertical stacking of NFETs and PFETs, providing an additional dimension for CMOS area scaling while improving device symmetry and simplifying the manufacturing process by defining p-n junction positions and channel lengths during initial processing steps.
Implementation Method 1
A semiconductor material is epitaxially grown within the trench to form a fin
Data Source
AI summary
A method of forming a semiconductor device and resulting structure in which a trench is formed extending through a plurality of layers on a semiconductor substrate. The plurality of layers includes a sequence of dielectric materials. A first portion of the plurality of layers corresponds to a bottom vertical field effect transistor (VFET) and a second portion of the plurality of layers corresponds to a top VFET. A sacrificial layer separates the bottom VFET from the top VFET. A fin is formed within the trench by epitaxially growing a semiconductor material. A hard mask is formed above a central portion of the plurality of layers. Portions of the plurality of layers not covered by the hard mask are removed. The first portion of the plurality of layers is covered to remove the sacrificial layer. The recess resulting from the removal of the sacrificial layer is filled with an oxide material.