Stacked Vertical Power Transistor Packages
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Solution Overview
Problem
Conventional packaging strategies for vertical power transistors in high-power applications result in large package sizes, increased electromagnetic interference (EMI), and parasitic resistance and inductance due to wirebonding, as well as complex PCB attachment issues caused by exposed lead frames switching between high and low voltages.
Innovation Solution
A semiconductor device configuration where two vertical transistors are stacked with source electrodes on the back surface and drain and gate electrodes on the top surface, utilizing flip-chip mounting to a lead frame with isolated plates, reducing package footprint and interconnection resistance and inductance, and allowing co-packaging of a control chip for improved thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional packaging strategy with side-by-side die arrangement and wirebonding is used, then ease of manufacture is maintained, but package size increases and parasitic resistance and inductance increase
Solution Approach 1:
The patent transitions from a planar side-by-side die arrangement to a vertical stacked configuration, utilizing the third dimension (height) to reduce the footprint area. Multiple power transistor dies are stacked one on top of another, with interconnections made through vertical vias and conductive layers instead of lateral wirebonds, thereby reducing package size while maintaining manufacturability.
Solution Approach 2:
The patent introduces an intermediary substrate or interposer layer that facilitates vertical stacking and provides conductive pathways for electrical interconnections between stacked dies. This intermediary structure enables direct vertical connections, replacing lateral wirebonds and reducing parasitic elements while maintaining ease of assembly.
2Ease of manufacture
If conventional packaging strategy with wirebonding is used, then ease of manufacture is maintained, but parasitic resistance and inductance increase
Solution Approach 1:
The patent introduces an intermediary substrate or interposer layer that facilitates vertical stacking and provides conductive pathways for electrical interconnections between stacked dies. This intermediary structure enables direct vertical connections, replacing lateral wirebonds and reducing parasitic elements while maintaining ease of assembly.
Solution Approach 2:
The patent replaces the mechanical wirebonding process with a semiconductor fabrication-based interconnection approach using vertical vias, conductive plugs, and metallization layers. This substitution eliminates the need for separate wirebonding steps and reduces parasitic resistance and inductance inherent in wirebond structures.
3Reliability
If exposed lead frame pieces are used for high-voltage connections, then electrical connectivity is achieved, but electromagnetic interference increases and PCB attachment becomes complex
Solution Approach 1:
The patent merges the lead frame structure with the stacked die assembly, integrating the heat sink and electrical interconnection functions into a unified structure. The lead frame serves as both the mechanical support and the electrical pathway, eliminating separate exposed lead frame pieces and reducing electromagnetic interference through improved shielding and grounding.
Solution Approach 2:
The patent makes the lead frame multi-functional, serving simultaneously as mechanical support, heat dissipation path, and electrical interconnection structure. This universal structure eliminates the need for separate exposed lead frame pieces for high-voltage connections, reducing EMI while maintaining electrical connectivity.
Data Source
AI summary
The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.