Stacked Vertical Transistor Gate Segmentation for Drive Current
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Solution Overview
Problem
Conventional vertical transistors have limited drive current for a given chip area, necessitating an enhancement in drive current for improved technology scaling.
Innovation Solution
A stacked vertical field effect transistor structure is developed, featuring a lower and upper functional gate structure with multiple source/drain regions, achieved through a method involving epitaxial growth and sacrificial gate replacement, to enhance drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional vertical transistor structure is used, then device simplicity is maintained, but drive current for given chip area is limited
Solution Approach 1:
The transistor channel is divided into multiple stacked segments (first channel portion, second channel portion, third channel portion) with separate gate structures controlling each segment. This segmentation allows independent optimization of each channel portion, increasing total drive current while maintaining manageable structural complexity through modular design
Solution Approach 2:
The invention transitions from a conventional single-plane transistor layout to a three-dimensional stacked configuration where multiple channel portions are arranged vertically. This dimensional change enables increased drive current by utilizing vertical space, effectively multiplying the current-carrying capacity without proportionally increasing chip area
2Productivity
If chip area is reduced for scaling, then integration density improves, but drive current capability decreases
Solution Approach 1:
By stacking multiple channel portions vertically, the invention achieves high integration density in a small footprint while maintaining high drive current. The vertical arrangement allows multiple current paths to be packed into a compact area, decoupling the trade-off between chip area and current capability
Solution Approach 2:
Multiple transistor components (gates, channels, source/drain regions) are nested vertically within a compact structure. The stacked configuration allows smaller individual components to be arranged in a nested fashion, achieving high density while preserving the current-carrying capacity of larger structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases drive current for a given chip area, addressing the limitations of conventional vertical transistors and enabling improved technology scaling.
Implementation Method 1
an first epitaxial doped semiconductor material layer is epitaxially grown from exposed sidewall surfaces of the middle portion of the semiconductor channel material pillar, and a second epitaxial doped semiconductor material layer is also epitaxially grown from exposed sidewall surfaces of an upper portion of the semiconductor channel material pillar
Implementation Method 2
An anneal is then performed to diffuse dopants from the bottom source/drain layer into a bottom portion of the semiconductor channel material pillar and to provide a bottom source/drain region, dopants from the first epitaxial doped semiconductor material layer into the middle portion of the semiconductor channel material pillar and to provide a middle source/drain region
Data Source
AI summary
A stacked vertical field effect transistor that has enhanced drive current is provided. The stacked vertical field effect transistor includes a lower functional gate structure located adjacent sidewall surfaces of a lower channel portion of a semiconductor channel material pillar. An upper functional gate structure is located above the lower functional gate structure and adjacent sidewall surfaces of an upper channel portion of the semiconductor channel material pillar. A bottom source/drain region is located beneath the lower functional gate structure, a middle source/drain region is located between the lower functional gate structure and the upper functional gate structure, and a top source/drain region is located above the upper functional gate structure.