Stacked Vertical Transistors With Common Source/Drain for High Voltage
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Solution Overview
Problem
As integrated circuits continue to miniaturize, there is a need for transistors to achieve higher drive currents with smaller dimensions, which existing semiconductor manufacturing processes struggle to address effectively, especially at sub-20 nm nodes and with non-planar device architectures like FinFET and vertical devices.
Innovation Solution
The method involves forming vertically stacked transistors with a common source/drain region, where each transistor has a unique channel and source/drain layer, and a metal semiconductor alloy is used to create a low resistance pathway between them, allowing for increased drive current and voltage compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistor dimensions are reduced to achieve higher drive currents, then drive current increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical transistor architecture, moving the current flow path from two-dimensional lateral movement to three-dimensional vertical movement. This dimensional change allows the transistor to achieve higher drive currents through increased channel length in the vertical direction while maintaining small lateral footprint, thereby improving drive current without requiring proportionally smaller lateral dimensions that would exacerbate manufacturing precision challenges.
Solution Approach 2:
The patent divides the transistor structure into multiple vertical segments including source region, channel region, and drain region stacked in the vertical direction. This segmentation allows each region to be independently optimized and formed through separate epitaxial growth steps, enabling precise control over the dimensions and properties of each segment while achieving overall high drive current through the stacked configuration.
2Power
If new device architectures like FinFET and vertical devices are employed, then drive current and voltage compatibility improve, but device complexity increases
Solution Approach 1:
The patent designs the vertical transistor structure with a common source/drain region that serves multiple functions: it acts as the drain for one transistor and the source for another transistor in the stacked configuration. This multi-functionality reduces the overall number of discrete source and drain regions needed, thereby reducing structural complexity while maintaining voltage compatibility and drive current performance across multiple transistor levels.
Solution Approach 2:
The patent merges the source/drain regions of adjacent transistors into a shared common source/drain structure. By combining what would traditionally be separate source and drain regions into a single shared region, the patent reduces the total number of interfaces and structural elements, simplifying the overall device architecture while enabling series connection of multiple transistors for high voltage operation.
3Area of stationary object
If vertically stacked transistors are formed, then area is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary epitaxial growth to form the complete multilayered fin structure including all source/drain layers and channel layers in the vertical stack before any gate formation or patterning steps. This preliminary formation of the vertical stack architecture allows subsequent processing steps to work with a pre-defined three-dimensional structure, reducing the complexity of later alignment and patterning operations that would be required if the vertical stack were formed incrementally.
Solution Approach 2:
The patent implements a nested structure where multiple transistor channels are vertically nested within a single lateral footprint, with each channel stacked above the previous one. This nesting arrangement allows multiple functional elements to occupy the same planar space in different vertical levels, achieving high device density and small footprint while the common source/drain regions provide structural consolidation that simplifies the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher drive currents and voltage compatibility in a smaller footprint, making vertically stacked transistors attractive for advanced node technologies like the 5 nm node and beyond, while maintaining efficient electrostatic control.
Implementation Method 1
A metal semiconductor alloy region is present extending along a sidewall of the common source/drain region extending from a first spacer on the first gate region to a second spacer on the second gate region
Data Source
AI summary
A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.