Stacked V-GAAFET IC Unit with Segmented Channel for Gate Length Control
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Solution Overview
Problem
It is challenging to control the gate length of Vertical Gate-all-around Field Effect Transistors (V-GAAFETs), particularly those with single-crystalline channel materials, and to manufacture high-performance Integrated Circuits (ICs) with stacked V-GAAFETs of different conductivity types while minimizing footprint and manufacturing costs.
Innovation Solution
The development of an Integrated Circuit (IC) unit based on stacked vertical nanowire devices, where the channel layer is recessed to allow for precise control of gate length through epitaxial growth, and the source/drain layers are designed to overlap the channel layer, enabling the stacking of multiple V-GAAFETs with different conductivity types without increasing the footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching timing is used to control gate length, then manufacturing process is simple, but gate length control precision deteriorates
Solution Approach 1:
The channel layer is segmented into distinct portions (first portion and second portion) separated by a gap, allowing independent control of gate length through the spacing between segments rather than relying on etching timing. This segmentation enables precise gate length definition while maintaining manufacturing feasibility.
Solution Approach 2:
The patent transitions from controlling gate length in the lateral dimension through etching timing to controlling it through vertical stacking and lateral spacing of separated channel portions. The gate length is defined by the distance between the first and second channel portions, introducing a new dimensional approach to gate length control.
2Reliability
If V-GAAFETs with single-crystalline channel material are used, then device performance is improved, but gate length control becomes more difficult
Solution Approach 1:
The single-crystalline channel layer is segmented into separate portions that can be independently positioned and controlled. This segmentation allows the high-performance single-crystalline material to be used while enabling precise gate length definition through the controlled spacing between channel portions, rather than relying on difficult-to-control etching processes.
3Productivity
If multiple V-GAAFETs with different conductivity types are stacked, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple V-GAAFETs with different conductivity types (n-type and p-type) are merged into a single vertical stack structure. The shared source/drain layers and common substrate provide a unified manufacturing platform that simplifies the production of multi-type device integrations while achieving high integration density through vertical stacking.
Solution Approach 2:
The stacked V-GAAFET structure serves multiple functions within a single footprint: it integrates different conductivity types (nFET and pFET), provides vertical channel transport, and enables complex logic functions. This multi-functional design achieves high productivity by consolidating multiple device types into one universal stack structure.
4Ease of manufacture
If planar device arrangement is used, then manufacturing is simpler, but footprint scaling deteriorates
Solution Approach 1:
The patent transitions from planar (2D) device arrangement to vertical (3D) stacking configuration. By arranging source/drain layers and channel structures in the vertical dimension rather than spreading them out laterally, the design achieves compact footprint while maintaining manufacturing simplicity through standardized vertical fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of gate length, reduces parasitic capacitance, and enables the integration of multiple V-GAAFETs with different conductivity types, resulting in improved device performance and reduced manufacturing costs, with the potential to save up to 30-40% of the area required in conventional CMOS designs.
Implementation Method 1
precise control of gate length through epitaxial growth
Data Source
AI summary
There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.