Stacked Electrode Via Layout for Breakdown Voltage and Chip Area
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in efficiently forming vias that connect interconnects across stacked electrode layers, leading to increased chip surface area and interconnect length, which affects operation speed and reliability.
Innovation Solution
The semiconductor device incorporates a conductive via that pierces a stacked body with an insulating film surrounding it, ensuring sufficient breakdown voltage and reduced chip surface area by optimizing the via's diameter and the recessed distance from adjacent layers, allowing for a thinner lower layer interconnect and shorter interconnect length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the via diameter is increased to ensure sufficient breakdown voltage, then reliability improves, but chip surface area increases
Solution Approach 1:
The patent applies nesting by placing the insulating film inside the via structure, surrounding the conductive via. This nested configuration allows the insulating film to provide breakdown voltage protection while occupying minimal space within the via, thereby maintaining reliability without significantly increasing chip surface area.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional via structure with the insulating film wrapped around the via. This dimensional change allows the breakdown voltage function to be achieved in the vertical and radial dimensions rather than requiring additional horizontal space, thus improving reliability without increasing chip surface area.
2Speed
If the interconnect length is reduced to enhance operation speed, then speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by providing the insulating film specifically at the via location where electrical breakdown risk is highest, rather than uniformly across the entire interconnect structure. This localized approach ensures sufficient breakdown voltage protection at critical points while allowing for more flexible via placement, thus enhancing operation speed without excessively increasing manufacturing precision requirements.
3Area of stationary object
If the lower layer interconnect is made thinner to reduce chip surface area, then area decreases, but structural integrity and current carrying capacity worsen
Solution Approach 1:
The patent applies composite materials by combining the lower layer interconnect with the insulating film structure around the via. This composite configuration allows the interconnect to be thinner while the insulating film provides additional structural support and electrical isolation, thus reducing chip surface area while maintaining structural integrity and current carrying capacity.
Data Source
AI summary
According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.