Stacked Via Structure for Stress-Resistant Fan-Out Packaging
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Solution Overview
Problem
The reliability of integrated fan-out packages, particularly in the semiconductor industry, is compromised due to stress-related via crack issues in the redistribution circuit structure fabricated on molding compounds, which affects the overall performance and durability of package-on-package (PoP) structures.
Innovation Solution
A stacked via structure is proposed, featuring conductive vias with tapered or vertical sidewalls and varying dimensions, aligned or offset in a specific pattern, to distribute stress evenly and enhance structural strength, along with a multi-layered redistribution wiring system to connect semiconductor dies efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional redistribution circuit structure is fabricated on molding compound, then the package achieves compactness and integration, but stress concentration causes via cracks that compromise reliability
Solution Approach 1:
The via structure is segmented into multiple stacked vias (first via, second via, third via) with different dimensions and orientations. This segmentation distributes the stress that would otherwise concentrate in a single via, preventing via cracks while maintaining the compact integrated fan-out package structure.
Solution Approach 2:
Different vias in the stacked structure have different local properties - varying diameters, depths, and orientations - to optimize stress distribution at each location. The first via has a larger diameter for primary connectivity, while subsequent vias have smaller diameters and different orientations to分散 stress concentration points.
2Productivity
If minimum feature size is reduced to increase integration density, then more components fit in a given area, but package size must be reduced which compromises structural strength
Solution Approach 1:
The via structure transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple vias are stacked vertically with different orientations (first via vertical, second via angled, third via horizontal), utilizing the third dimension to achieve stress distribution without increasing lateral footprint, thus maintaining high integration density while improving structural strength.
3Ease of manufacture
If via dimensions are uniform for simplicity of fabrication, then manufacturing is easier, but stress concentration occurs leading to via cracks
Solution Approach 1:
The via parameters (diameter, depth, orientation angle) are deliberately changed across the stacked via structure. The first via has diameter D1 and vertical orientation, the second via has diameter D2 and angled orientation, and the third via has diameter D3 and horizontal orientation. These parameter variations optimize stress distribution while remaining manufacturable through standard semiconductor fabrication processes.
Data Source
AI summary
A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.