Stacked Via Interconnect Inductor Layout for Higher Q in Small Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for smaller packages with improved performance in electronic devices, particularly in inductors, which require higher Q factors and larger apertures to enhance inductance while maintaining reliability and reducing delamination risks.
Innovation Solution
The solution involves a device comprising stacked device portions with via interconnects in encapsulation layers, where solder interconnects are offset to increase the aperture size and reduce delamination, utilizing dielectric and magnetic layers to enhance inductance and Q factors, and incorporating pillar interconnects for improved structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar inductor design is used, then manufacturing is simpler, but aperture size is limited and Q factor is reduced
Solution Approach 1:
The patent transitions from a planar two-dimensional inductor design to a three-dimensional stacked structure with multiple layers and via interconnects. This dimensional change enables larger effective aperture area without increasing the planar footprint, thereby improving Q factor and inductance while maintaining a compact form factor suitable for mobile devices.
Solution Approach 2:
The patent implements a nested structure where multiple device portions are stacked vertically with via interconnects penetrating through encapsulation layers to connect corresponding interconnects across layers. This nesting approach maximizes the use of vertical space to achieve larger effective aperture while maintaining a compact overall package size.
2Reliability
If larger aperture inductors are created to improve Q factor, then inductance increases, but package size increases
Solution Approach 1:
By stacking device portions vertically and using via interconnects to connect corresponding interconnects across layers, the patent achieves a larger effective aperture area in the vertical dimension without increasing the horizontal package footprint. This allows high Q factor inductors to be implemented in compact packages suitable for mobile devices.
Data Source
AI summary
A device comprising (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as an inductor.