Stacked Via Interconnect Extension for Electromigration Resistance
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Solution Overview
Problem
In semiconductor devices, the miniaturization of interconnects and vias leads to increased current density, causing electromigration (EM) due to current concentration and Joule heat generation, which reduces EM resistance and limits the allowable current density.
Innovation Solution
A stacked via structure is designed with an extension part of the interconnect that is more than six times the width of the via, allowing effective dissipation of Joule heat and reducing temperature increases, thereby enhancing EM resistance without increasing via width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the via width is increased to reduce current density, then EM resistance is improved, but the device area increases and miniaturization is compromised
Solution Approach 1:
The invention transitions from a two-dimensional via structure to a three-dimensional stacked via structure by adding via layers vertically. Multiple via layers are stacked to form parallel current paths, increasing the effective current-carrying capacity without increasing the lateral area of individual vias. This dimensional transition allows high current density to be distributed across multiple stacked vias, improving EM resistance while maintaining miniaturization.
Solution Approach 2:
The current path is segmented into multiple via layers stacked vertically. Instead of using a single wide via, the invention divides the current flow into multiple narrower vias arranged in stacked layers. Each via carries a portion of the total current, and the segmentation is achieved by creating multiple via layers with interconnects between them, effectively splitting the current load to reduce EM effects.
2Reliability
If multiple via layers are stacked to increase current capacity, then current density is reduced, but Joule heat generation increases due to current concentration in lower vias
Solution Approach 1:
The invention applies different structural characteristics to different via layers to optimize heat dissipation. Specifically, the lower via layer (which experiences higher current concentration and heat generation) is designed with a larger via diameter or different material composition compared to upper via layers. This local quality variation allows the lower via to handle higher thermal loads while upper vias maintain standard dimensions, effectively managing Joule heat distribution across the stacked structure.
Solution Approach 2:
Intermediate interconnects are introduced between stacked via layers to serve as thermal and electrical mediators. These interconnects provide additional current paths that distribute current more evenly across the via stack, preventing excessive current concentration in lower vias. The intermediary interconnects also facilitate heat dissipation by providing thermal conduction paths, reducing the temperature rise caused by Joule heating in the lower via layers.
3Reliability
If via length is increased to relieve current concentration, then current distribution is improved, but manufacturing complexity and via resistance increase
Solution Approach 1:
Instead of increasing via length in the vertical direction (which would increase via resistance and manufacturing complexity), the invention distributes current paths into multiple via layers stacked vertically. Each via maintains a reasonable length, but the overall current capacity is achieved by stacking multiple such vias with interconnects. This approach improves current distribution without excessively increasing individual via dimensions or manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases EM resistance, allowing higher current flow without increasing via width, while effectively dissipating heat and reducing EM occurrence.
Implementation Method 1
Joule heat is generated in the via part, and a temperature rises in a particular part
Implementation Method 2
the first interconnect has a first extension part extending from a position of an end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect
Data Source
AI summary
A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.