Stacked Via Structure for Self-Aligned Multi-Pitch Interconnects

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Solution Overview

Problem

The challenge of optimizing the performance of interconnects in semiconductor devices, particularly transition vias, which provide electrical connectivity between metal layers of different pitches, is exacerbated by the need for advanced fabrication processes and increased density in integrated circuits.

Innovation Solution

The formation of stacked vias with bottom portions using subtractive patterning, where the bottom via portion is self-aligned to the bottom conductive line and the top via portion is formed using Damascene fabrication, enabling efficient electrical connectivity between metal layers of varying pitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional via formation processes are used to connect metal layers of different pitches, then electrical connectivity is achieved, but fabrication complexity increases and manufacturing precision deteriorates

Engineering Contradiction:
Improveelectrical connectivityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via formation process is segmented into two distinct operations: (1) forming bottom via portions using subtractive patterning that are self-aligned to bottom conductive lines, and (2) forming top via portions using Damascene fabrication that are self-aligned to top conductive lines. This segmentation allows each via portion to be independently optimized and aligned to its respective conductive layer, reducing overall fabrication complexity while maintaining connectivity reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bottom via portions are formed in advance using subtractive patterning before the top via portions are created. This preliminary action establishes a foundation that simplifies subsequent alignment steps and reduces the complexity of the overall via formation process by pre-positioning critical alignment features.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If advanced fabrication processes are used to optimize interconnect performance, then connectivity between metal layers of different pitches is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improveinterconnect performanceVSAvoidvia alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The subtractive patterning process is designed to be self-aligned to the bottom conductive lines, and the Damascene fabrication is self-aligned to the top conductive lines. This self-alignment mechanism eliminates the need for complex external alignment procedures, thereby maintaining manufacturing precision while enabling advanced interconnect performance optimization.

Inventive Principle:
Principle #25Self-service

3Quantity of substance

If via density is increased to support higher circuit density, then functional unit density is improved, but fabrication complexity increases

Engineering Contradiction:
Improvevia densityVSAvoidfabrication process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By segmenting via formation into separate bottom and top portions with different fabrication methods, the process can accommodate higher via densities without proportionally increasing complexity. Each portion can be independently patterned and formed using optimized processes for its specific requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different fabrication methods are applied to different portions of the via structure: subtractive patterning for bottom via portions and Damascene fabrication for top via portions. This local quality approach allows each region to be optimized for its specific functional requirements, enabling higher overall via density without uniform complexity increases.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4057328B1Stacked vias with bottom portions formed using subtractive patterning
Publication Date: 2026.03.04 INTEL CORP
  • EP4057328B1 patent drawingFigure 1
  • EP4057328B1 patent drawingFigure 2A
  • EP4057328B1 patent drawingFigure 2B

AI summary

Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a "stacked via"). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene fabrication.