Stacked Semiconductor Via Structure to Reduce Plasma Etch Damage
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Solution Overview
Problem
The formation of vias in thick silicon substrates during semiconductor manufacturing can cause plasma-induced damage (PID), affecting transistor characteristics, increasing leakage current, and reducing yield due to the deepening of vias.
Innovation Solution
A semiconductor apparatus is designed with a first base substrate having a shallow via and a second base substrate with a deep via formed separately, where the second base substrate is thicker than the first via, and both are electrically connected using a conductive material, reducing the impact on the logic circuit of the first base substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via is formed in a thick silicon substrate using dry etching, then electrical connection is achieved, but plasma-induced damage occurs affecting transistor characteristics
Solution Approach 1:
The substrate is divided into two separate base substrates (first and second base substrates) stacked together. The via formation process is segmented such that the first via is formed in the first base substrate and the second via is formed in the second base substrate separately. This segmentation allows each via to be formed with appropriate etching depth control, preventing plasma-induced damage to transistors in the first base substrate while maintaining electrical connection functionality.
2Reliability
If the via depth is increased to achieve electrical connection through thick substrate, then connection is established, but PID impact increases
Solution Approach 1:
The via formation process transitions from a single vertical dimension in one thick substrate to a distributed structure across two stacked substrates. The first via extends from the front surface toward the back surface of the first base substrate, while the second via is formed in the second base substrate. This dimensional redistribution allows electrical connection to be achieved without requiring excessively deep etching in any single substrate, thereby reducing plasma-induced damage.
3Area of stationary object
If via etching is performed to connect pad electrode inside chip, then area is reduced, but transistor characteristics are affected
Solution Approach 1:
The chip structure is segmented into two separate base substrates that are bonded together. The first base substrate contains the pixel region and pad electrode, while the second base substrate contains the logic circuit. The via formation is segmented accordingly, with the first via formed in the first base substrate and the second via formed in the second base substrate. This segmentation enables compact area utilization while protecting transistor characteristics by controlling etching depth in each substrate separately.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the impact of PID on transistor characteristics, reducing threshold voltage changes and increasing yield by separating the via formation and using a thicker second base substrate to mitigate stress effects.
Implementation Method 1
a second via through which the connection portion and an electrode situated in a lowest surface of the second base substrate are electrically connected to each other using a conductive material
Data Source
AI summary
To reduce an impact due to dry etching performed when a via is formed in a substrate. A first base substrate includes first and second semiconductor substrates. A pixel region is formed on the first semiconductor substrate. A logic circuit that processes a pixel signal output from the pixel region is formed on the second semiconductor substrate. The first base substrate includes a first via that passes through a wiring layer of the logic circuit to a back surface of the first base substrate. A second base substrate includes a connection portion and a second via. The connection portion is connected to the first via of the first base substrate on a front surface of the second base substrate. The connection portion and an electrode situated in a lowest surface of the second base substrate are electrically connected to each other through the second via using a conductive material.