Stacked Via Structure for Stress-Resistant PoP Redistribution
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Solution Overview
Problem
The reliability of the redistribution circuit structure in integrated fan-out packages, particularly in package-on-package (PoP) structures, is a concern due to issues with stress concentration leading to via cracks, which affects the structural integrity and performance of the compact semiconductor packaging.
Innovation Solution
A stacked via structure is proposed, where conductive vias with tapered or vertical sidewalls are embedded in dielectric layers, and redistribution wirings are strategically positioned to distribute stress evenly, enhancing structural strength and minimizing crack formation by varying the width and contact area of each via layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution circuit structures are used in integrated fan-out packages, then compactness is achieved, but stress concentration leads to via cracks reducing reliability
Solution Approach 1:
The redistribution circuit structure is segmented into multiple stacked via layers (first via layer, second via layer, third via layer) with different via widths. This segmentation allows stress to be distributed across multiple interfaces rather than concentrated at a single via interface, thereby reducing the risk of via cracks and improving overall structure reliability.
Solution Approach 2:
Different via widths are used at different locations and layers of the stacked via structure. The first via layer has a first width, the second via layer has a second width different from the first, and the third via layer has a third width different from the second. This local variation in via dimensions optimizes stress distribution at each interface, preventing stress concentration and enhancing reliability.
2Reliability
If via width is varied in stacked via structure, then stress distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The via width parameter is changed across different via layers to optimize stress distribution. The first via layer has a first width, the second via layer has a second width, and the third via layer has a third width, with each subsequent via having a smaller width than the previous layer. This parameter variation is implemented in a systematic manner that improves structural integrity while maintaining manufacturability through controlled geometric progression.
Data Source
AI summary
A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.