Stacked Via Sidewall Structure for Misalignment-Tolerant Interconnects
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Solution Overview
Problem
Conventional stacked via structures in semiconductor devices face misalignment issues between upper and lower vias, leading to potential electrical signal disruptions and increased manufacturing costs due to the need for larger via widths and additional processing steps.
Innovation Solution
The implementation of a stacked via structure with a conductive sidewall at the upper end of the lower via or the lower end of the upper via to ensure alignment margin, formed through deposition and etching without a separate mask pattern, allowing for efficient process integration in both peripheral and cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of the vias is made large to prevent misalignment, then alignment stability is improved, but the overall device size increases
Solution Approach 1:
The patent introduces a sidewall structure that extends vertically from the via body, adding a dimensional element that provides alignment tolerance without increasing the horizontal via width. The sidewall creates an overlapping region between upper and lower vias in the vertical dimension, ensuring electrical connection even when horizontal alignment is imperfect.
Solution Approach 2:
The sidewall is formed in advance before the upper via is created, establishing a protective and alignment-tolerant structure that guides subsequent processing steps. The sidewall's presence before upper via formation ensures that the upper via can be aligned more easily to the lower via's extended structure.
2Manufacturing precision
If additional masks or high-performance equipment are used to accurately perform the via formation process, then misalignment is prevented, but manufacturing costs significantly increase
Solution Approach 1:
The sidewall structure serves multiple functions simultaneously: it provides alignment tolerance, ensures electrical connection between vias, and acts as a self-aligned feature that reduces dependency on high-precision masking processes. The structure essentially performs the alignment function that would otherwise require additional masks or equipment.
3Manufacturing precision
If a sidewall is formed in both peripheral and cell regions, then alignment margin is ensured, but process efficiency decreases
Solution Approach 1:
The patent applies the sidewall formation selectively based on local requirements. Sidewalls are formed in peripheral regions where alignment margins are critical for device functionality, while cell regions may use simplified via structures where standard alignment processes are sufficient. This localized approach maintains alignment where needed while preserving overall process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures a sufficient alignment margin between upper and lower vias, prevents process efficiency deterioration, reduces additional processing requirements, and maintains device size and manufacturing cost effectiveness.
Implementation Method 1
forming a sidewall containing a conductive material at an upper end of the lower via or a lower end of the upper via
Implementation Method 2
formed through deposition and etching without a separate mask pattern
Data Source
AI summary
Provided is a stacked via structure, a semiconductor device including the stacked via structure and a method of manufacturing the same. More particularly, proposed is a stacked via structure, a semiconductor device including the stacked via structure and a method of manufacturing the same, which ensure an alignment margin between upper and lower vias by forming a conductive sidewall at an upper end of the lower via or a lower end of the upper via to surround the upper or lower end.