Stacked Vias in FO-WLCSP Interconnects for Laser Ablation Margin
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Solution Overview
Problem
Conventional fan-out wafer level chip scale packages (Fo-WLCSP) face manufacturing defects due to the use of lasers for removing insulating layers, which can penetrate underlying conductive layers, increasing costs and defect rates.
Innovation Solution
The development of a semiconductor device with a robust interconnect structure that includes stacked vias within the encapsulant, allowing for a design margin during laser removal of insulating material without penetrating the conductive layers, achieved through multiple insulating and conductive layers with strategically formed vias and conductive layers extending through the encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If laser is used to remove insulating layers during formation of topside and bottom-side build-up interconnect structures, then insulating material can be removed efficiently, but the laser may penetrate through the underlying conductive layer causing manufacturing defects
Solution Approach 1:
The patent applies preliminary action by forming a stacked via structure with multiple insulating layers and conductive layers before the laser removal process. The conductive layers are pre-positioned to create a buffer zone that prevents laser penetration damage to underlying conductive structures, thereby enabling efficient laser-based insulating material removal while preserving conductive layer integrity
Solution Approach 2:
The stacked via structure with multiple conductive layers acts as a cushioning layer before the laser removal process. This pre-positioned conductive layer structure absorbs or blocks excessive laser energy, preventing it from penetrating through and damaging underlying conductive layers, thus protecting the structural integrity during high-efficiency insulating material removal
2Reliability
If topside and bottom-side build-up interconnect structures are formed, then electrical interconnect is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of topside and bottom-side build-up interconnect structures into a single integrated process. By combining these operations and using the stacked via structure to serve multiple functions (both electrical interconnection and laser protection), the manufacturing process is simplified, reducing overall manufacturing cost while maintaining electrical interconnect reliability
3Device complexity
If conventional Fo-WLCSP structure is used, then manufacturing process is simpler, but manufacturing defects increase due to laser penetration
Solution Approach 1:
The patent implements a nested structure where multiple insulating layers and conductive layers are arranged in a stacked via configuration. The inner conductive layers are nested within outer insulating layers, creating a protective configuration that prevents laser penetration defects while maintaining a relatively simple overall manufacturing process flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces manufacturing defects and costs by providing a design margin for laser removal of insulating material, ensuring the integrity of the conductive layers and enhancing the reliability of the interconnect structure in Fo-WLCSPs.
Implementation Method 1
encapsulant deposited over and around the semiconductor die
Implementation Method 2
a laser is commonly used to remove portion of the insulating layers. The laser is known to penetrate through the underlying conductive layer
Data Source
AI summary
A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.