3D Stacked Voltage Regulator for Higher Current and Voltage Gaps
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Solution Overview
Problem
Current voltage converters face challenges in efficiently handling increasing domain currents and input-to-output voltage gaps while maintaining conversion efficiency, due to constrained on-die passive volume and lower voltage ratings of transistors and capacitors.
Innovation Solution
The solution involves 3D stacking of multiple silicon wafers or dice with passive and active components, forming a larger voltage regulator structure that increases passive volume and switch conductance per unit area, allowing for higher input voltages and output current capabilities, and incorporating different process technologies for improved high-voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacking of multiple wafers or dice is implemented, then passive volume and switch conductance per unit area increase, but device complexity increases
Solution Approach 1:
The patent transitions from traditional 2D planar voltage regulator design to 3D stacked architecture, stacking multiple wafers or dice vertically to increase passive volume and switch conductance per unit area. This dimensional change allows components to be distributed across multiple layers, achieving higher power density without proportionally increasing footprint area.
2Loss of energy
If components are distributed on multiple wafers or dice, then routing losses reduce, but manufacturing precision requirements increase
Solution Approach 1:
The voltage regulator is segmented into multiple independent wafers or dice that can be manufactured separately using standard fabrication processes. Each wafer/die contains specific components (e.g., passives on one wafer, active devices on another), allowing modular assembly. This segmentation reduces routing losses by placing components closer together in 3D space while enabling relaxed manufacturing precision requirements through separate fabrication and assembly.
3Loss of energy
If higher input voltages are enabled, then conversion efficiency improves, but reliability decreases due to higher stress on components
Solution Approach 1:
The 3D stacked architecture enables higher input voltage operation by distributing voltage stress across multiple series-connected device stacks in the vertical dimension. Each individual transistor or capacitor experiences reduced voltage stress compared to a 2D design, improving reliability while maintaining high conversion efficiency through optimized power conversion paths.
Data Source
Figure 1A~3
Figure 4~5B
Figure 6A~6B
AI summary
Embodiments herein relate to a voltage regular (VR) formed by components which are distributed over a stack of dice or wafers. Separate VRs can be provided in separate dice or wafers, where their outputs are coupled at an output path. A common control circuit can be used to control each VR. Passive components of a VR can be distributed on separate dice. For example, capacitors or inductors on the different dice or wafers can be coupled in parallel or in series, respectively. The stack can include dice or wafers of different types, such as silicon and Gallium Nitride. A first VR on a first type of die or wafer can be arranged in cascade with a second VR on a second type of die or wafer. The components in the different dice or wafers can be coupled by vias such as through-silicon vias.