Stacked Voltage Regulator Package Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip package structures result in large package areas and high manufacturing costs due to the need for multiple independent components, leading to inefficient use of space and increased costs.
Innovation Solution
A stacked package method for a voltage regulator is developed, integrating a gate driving circuit with a power switch on one chip and a second power switch on another, using bumps for electrical coupling, and employing non-conductive and conductive layers with leadframes to reduce size and increase integration density, eliminating the need for bonding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent components are used in a multi-chip package structure, then functional integration is achieved, but package area increases and manufacturing cost rises
Solution Approach 1:
The patent transitions from a planar multi-chip arrangement to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through through-silicon vias (TSVs), enabling functional integration while significantly reducing the horizontal package footprint. This vertical integration approach allows multiple functional components to coexist in a compact volume, directly resolving the contradiction between functional integration and package area.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked within a single package substrate, with each chip containing functional components. The chips are interconnected through TSVs that pass through the substrate, creating a compact nested arrangement. This nesting approach enables high functional integration density while minimizing the overall package area, effectively addressing the contradiction between versatility and area.
2Reliability
If multiple independent components are arranged coplanar on a carrier, then electrical coupling is achieved through bonding wires, but package area becomes larger than the sum of chip areas
Solution Approach 1:
The patent extracts and eliminates the bonding wire interconnection method, replacing it with direct vertical electrical coupling through TSVs. By removing the horizontal bonding wire routing layer, the design achieves reliable electrical coupling between stacked chips without requiring additional horizontal space for wire bonds, thus reducing package area while maintaining electrical connectivity.
Solution Approach 2:
The patent replaces the mechanical bonding wire system with an integrated vertical conduction path through TSVs. This substitution eliminates the need for separate bonding wire components and their associated routing space, achieving both reliable electrical coupling and compact package area through a more integrated structural approach.
3Adaptability or versatility
If independent chips are packaged separately and then encapsulated together, then functional modularity is maintained, but the ratio of chip footprint to package area decreases
Solution Approach 1:
The patent merges multiple independent functional chips into a single integrated three-dimensional package structure. By stacking chips vertically and interconnecting them through TSVs within a unified substrate, the design maintains functional modularity while achieving a chip footprint to package area ratio approaching 1, as the entire assembly occupies minimal horizontal space compared to separate packaging approaches.
Data Source
AI summary
The present disclosure relates to a stacked package of a voltage regulator and a method for fabricating the same. The method comprises: providing a first chip and a second chip which are integrated with each other, the first chip and the second chip each having a front surface provided with a plurality of bumps; forming a non-conductive layer and a conductive layer side by side on the back surface of the second chip; providing a first leadframe and a second leadframe each having at least a group of leads, the plurality of bumps on the first chip being electrically coupled to the first leadframe, the plurality of bumps on the second chip being electrically coupled to the second leadframe, and the back surface of the second chip being electrically coupled to a back surface of the first leadframe; the first leadframe being electrically coupled to the second leadframe; the first chip, the second chip, the conductive layer, the non-conductive layer, the bumps, the first leadframe, and the second leadframe forms a stacked package to reduce the footprint of a chip and reducing manufacture cost.