Stacked Vertical Transport FET EEPROM Devices
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Solution Overview
Problem
Existing CMOS devices and EEPROMs face challenges in minimizing space and complexity while maintaining efficient read/write functionality, particularly in the integration of n-type and p-type vertical transport field effect transistors.
Innovation Solution
A vertically stacked configuration of n-type and p-type vertical transport field effect transistors is implemented, with a common floating gate and specific dielectric materials like Si3N4, Y2O, or HfO2 for carrier injection, allowing for reduced chip area and complexity by enabling hot carrier injection for programming and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar CMOS devices are used, then manufacturing process is simpler, but chip area is larger and device density is lower
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertical 3D structures by stacking multiple transistor layers vertically. Each transistor layer includes source/drain regions, channel regions, and gate electrodes arranged in vertical succession, enabling higher device density within the same chip footprint while maintaining manufacturability through adapted fabrication processes
2Area of moving object
If vertical stacking of n-type and p-type VT FETs is implemented, then chip area is reduced by half, but manufacturing precision requirements increase
Solution Approach 1:
The vertical transistor stack is segmented into distinct functional layers including alternating n-type and p-type transistor layers, each with its own source/drain, channel, and gate structures. This segmentation allows independent optimization and fabrication of each layer type while maintaining overall device functionality and reducing the cumulative impact of alignment variations
Solution Approach 2:
Multiple transistor layers are merged into a single vertical stack structure where n-type and p-type transistors share common substrates and interlayer dielectric regions. This merging achieves high device density while using standardized fabrication processes that maintain reasonable precision requirements through process integration
3Productivity
If stacked VT FET configuration is used, then device density increases, but read/write functionality complexity increases
Solution Approach 1:
The stacked VT FET structure implements a universal cell design where alternating n-type and p-type transistor layers provide both read and write functionality through their complementary characteristics. The vertical stacking enables multiple transistors to share common bit lines and word lines, allowing a single stack to perform multiple logic functions and reducing the overall complexity of read/write operations compared to separate dedicated structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces chip area by half, lowers costs, and simplifies chip complexity while maintaining efficient read/write functionality through vertical integration, enabling effective programming and erasing of data.
Implementation Method 1
allowing for reduced chip area and complexity by enabling hot carrier injection for programming and erasing
Data Source
AI summary
A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.