Staggered-Pitch Stacked VTFET Layout for Straight Gate Contacts
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Solution Overview
Problem
Conventional vertically stacked vertical transport field-effect transistors (VTFETs) face challenges in achieving efficient electrical performance and manufacturing yields due to the need for complex gate contact formation processes, including lateral etching and horizontal jogs, which result in wiring blockages and reduced device density.
Innovation Solution
The semiconductor structure features vertically stacked VTFETs with a horizontal offset of half the contacted gate pitch between transistors, allowing for straight, vertical gate contacts that connect directly to interconnect wiring without horizontal jogs, simplifying the manufacturing process and improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertically stacked VTFETs are used with direct alignment, then device density is increased, but manufacturing complexity increases due to required lateral etching and horizontal jogs
Solution Approach 1:
The patent introduces a horizontal offset between vertically stacked VTFETs in different semiconductor layers. Specifically, VTFETs in upper layers are positioned at a horizontal distance of one-half contacted gate pitch relative to VTFETs in lower layers. This asymmetric positioning eliminates the need for lateral etching and horizontal jogs in gate contact formation, thereby reducing manufacturing process complexity while maintaining high device density.
2Quantity of substance
If lateral etching and horizontal jogs are used for gate contact formation, then vertical stacking is achieved, but wiring blockages occur and electrical performance deteriorates
Solution Approach 1:
By positioning VTFETs in upper layers at a horizontal offset of one-half contacted gate pitch relative to lower layers, the patent enables straight vertical gate contacts without lateral etching or horizontal jogs. This eliminates wiring blockages that would otherwise occur in conventionally aligned stacked structures, thereby improving electrical performance while maintaining vertical stacking density.
Solution Approach 2:
The patent resolves the conflict between vertical stacking and wiring connectivity by utilizing the horizontal dimension. The one-half contacted gate pitch offset in the horizontal plane allows vertical gate contacts to pass through intermediate structures without obstruction, effectively using horizontal positioning to solve a vertical integration problem.
3Ease of manufacture
If straight vertical gate contacts are implemented, then manufacturing process is simplified, but transistor layout flexibility is reduced
Solution Approach 1:
The patent establishes a universal layout rule where VTFETs in upper layers are positioned at a horizontal offset of one-half contacted gate pitch relative to lower layers. This universal positioning scheme enables straight vertical gate contacts for all stacked VTFETs regardless of their specific location on the chip, providing both manufacturing simplicity and layout flexibility through a repeatable pattern.
Data Source
AI summary
An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.