Stacked VTFETs with Sacrificial Oxide Patterning

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Solution Overview

Problem

Conventional fabrication techniques face challenges in scaling down integrated circuit devices, particularly in forming stacked vertical transport field-effect transistors (VTFETs) due to difficulties in middle-of-line (MOL) metal connection and patterning processes, which hinder further miniaturization and density improvements.

Innovation Solution

A sacrificial oxide patterning process is employed during the fabrication of stacked VTFETs to enable improved and simplified patterning for later metal fill, allowing for the formation of contacts to source/drain regions, thereby facilitating more efficient integration and denser circuit layouts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication techniques are used for scaling down integrated circuit devices, then manufacturing processes become more complex, but device size reduction and density improvement are hindered

Engineering Contradiction:
Improvedevice size reductionVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A sacrificial oxide layer is formed in advance on the semiconductor surface before subsequent patterning steps. This preliminary oxidation creates a defined starting point for contact formation, enabling precise control over contact hole positions and dimensions while simplifying the overall patterning sequence for MOL metal connections in stacked VTFETs

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial oxide layer acts as an intermediary material that facilitates the patterning process. It serves as a temporary structure that defines contact regions, enables selective etching, and guides subsequent metal deposition, thereby reducing the complexity of direct patterning on the semiconductor substrate

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If stacked vertical transport field-effect transistors are formed with conventional methods, then device density is limited, but middle-of-line metal connection and patterning become increasingly difficult

Engineering Contradiction:
Improvedevice densityVSAvoidmetal connection formation
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The fabrication process is segmented into distinct stages: sacrificial oxide formation, contact hole patterning, metal deposition, and sacrificial oxide removal. This segmentation allows each step to be optimized independently, making MOL metal connections in densely packed stacked VTFETs more manageable and manufacturable

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sacrificial oxide layer is selectively removed after metal contact formation to expose the semiconductor surface. This extraction of the temporary sacrificial material enables subsequent processing steps while having already facilitated precise metal connection formation in the high-density stacked VTFET structure

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20200303263A1Stacked vertical field-effect transistors with sacrificial layer patterning
Publication Date: 2020.09.24 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20200303263A1 patent drawing
  • US20200303263A1 patent drawing
  • US20200303263A1 patent drawing

AI summary

A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure and a sacrificial layer in contact with a source/drain region of the stacked vertical transport field-effect transistor structure. A masking layer is formed over the sacrificial layer. The masking layer defines a pattern to be patterned into the sacrificial layer. The sacrificial layer is patterned based on the masking layer to form a patterned sacrificial layer and the masking layer is removed. A portion of the stacked VTFET structure is etched down to a surface of the patterned sacrificial layer and the patterned sacrificial layer is removed to form a channel exposing the source/drain region. A contact material is formed in the etched portion of the stacked vertical transport field-effect transistor structure and in the channel. The contact material is formed in contact with the exposed source/drain region.