Stacked VTFET Logic Gates With Shared Epitaxial Layers
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturization and area scaling for vertical transport field-effect transistors (VTFETs), particularly in stacking planar FETs, which limits further device scaling and integration density.
Innovation Solution
The development of stacked VTFET structures with shared epitaxial layers, where vertical fins have bottom, top, and shared epitaxial layers, along with connecting layers, to form logic gates such as inverters, NAND, and NOR gates, allowing for increased channel density and reduced area without requiring insulation between fin channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar FET stacking is used, then device integration density can be increased, but area scaling is limited due to required insulation between fin channels
Solution Approach 1:
The patent merges the source/drain regions of stacked FETs by using a shared epitaxial layer that serves as the drain for the upper FET and the source for the lower FET. This eliminates the need for separate insulation layers between fin channels, reducing the top-down area while maintaining integration density. The connecting layer further merges the electrical pathways, allowing direct contact between the shared epitaxial layer and external circuits.
Solution Approach 2:
The patent transitions from a planar stacking approach to a vertical stacking approach with three-dimensional epitaxial layers. By growing epitaxial regions in the vertical dimension that wrap around fin structures, the design achieves higher integration density without proportionally increasing the planar footprint, effectively utilizing the vertical dimension to reduce area requirements.
2Productivity
If device size is reduced for miniaturization, then performance and power efficiency improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the FET structure into distinct vertical regions (upper and lower FETs) that share common components. This segmentation allows each region to be optimized independently for miniaturization while the shared epitaxial layers provide natural alignment references that simplify manufacturing precision requirements. The modular segmented structure makes it easier to control feature sizes at reduced dimensions.
Solution Approach 2:
The patent changes the dimensional parameters by transitioning from two-dimensional planar features to three-dimensional vertical structures. The epitaxial layers are grown with controlled thickness and wrap-around geometry, providing precise dimensional control through epitaxial growth parameters rather than lithographic patterning, which becomes increasingly difficult at scaled dimensions.
3Quantity of substance
If more FET channels are stacked vertically, then channel density increases, but structural complexity increases
Solution Approach 1:
The shared epitaxial layer serves multiple functions simultaneously: it acts as the drain region for the upper FET, the source region for the lower FET, and provides a common electrical connection point. The connecting layer also performs multiple functions by contacting both the shared epitaxial layer and external circuitry. This multi-functionality increases channel density without proportionally increasing structural complexity.
Solution Approach 2:
The patent implements a nested structure where the shared epitaxial layer is positioned between and connects the upper and lower FET structures. The epitaxial layer wraps around the fin channels in a nested configuration, with the connecting layer nested within the overall device structure. This nested arrangement efficiently packs more channels into the vertical space without creating excessive external complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a 33% reduction in top-down area for the same effective width, enabling improved performance and integration density in VTFETs, and allows for further scaling beyond conventional limits without sacrificing effective width.
Implementation Method 1
forming a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins
Data Source
AI summary
A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.