Stacked Double-Length VTFET Layout With Shared Source/Drain Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device fabrication is to increase device density while managing the complex connections required for vertical transfer field effect transistors (VTFETs), as their vertical orientation necessitates both top and bottom side connections, leading to space inefficiency and reduced device density.
Innovation Solution
The solution involves arranging VTFETs in layers with shared bottom source/drain structures and using conductive vias to connect devices, minimizing top-side connections and optimizing power/ground connections to enhance areal density, allowing for more devices within a given chip footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If VTFETs are arranged with individual top and bottom connections, then device functionality is ensured, but device density decreases due to space occupied by additional vias
Solution Approach 1:
The patent merges multiple VTFET devices into a stacked configuration where multiple devices share common source/drain regions and power/ground connections. This combining approach reduces the total number of individual vias needed while maintaining proper electrical connections for all devices, thereby increasing device density without sacrificing functionality
Solution Approach 2:
The shared source/drain structures serve multiple functions simultaneously: they act as electrical connections for multiple VTFETs, provide power/ground distribution, and reduce the overall via count. This multi-functionality allows a single structural element to serve several purposes, improving both density and connection efficiency
2Reliability
If more vias are used to connect VTFETs to power/signal planes, then electrical connections are improved, but available space for additional VTFETs decreases
Solution Approach 1:
Multiple VTFET devices are combined into vertical stacks that share common source/drain regions and power/ground connections. This merging reduces the total via count from N individual vias to fewer shared vias, freeing up chip area while maintaining reliable electrical connections for all devices in the stack
3Adaptability or versatility
If VTFETs are connected in serial or parallel configurations, then circuit functionality is achieved, but connection complexity increases
Solution Approach 1:
The patent transitions from planar device arrangements to three-dimensional stacked configurations. This dimensional change allows serial and parallel connections to be achieved through vertical stacking rather than lateral routing, simplifying the connection topology while maintaining circuit functionality and reducing layout complexity
Data Source
AI summary
Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.