Stacked Wafer Storage Architecture for Wider Bank-Level Access
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Solution Overview
Problem
The capacity and bit width of mainstream memories are limited by the proportional relationship between the number of banks in the die and the size of the I/O circuit, and the bit width is constrained by the bus connection, hindering further expansion.
Innovation Solution
A storage system is designed with stacked wafers, where a storage medium wafer is connected to a medium controller, allowing direct control of banks and utilizing sub-controllers to efficiently process data access instructions, with flexible connectivity options between sub-controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the die and I/O circuit are packaged in CUA architecture, then the storage can be formed with vertical stacking or side-by-side arrangement, but the quantity of banks in the die is proportional to the size of the I/O circuit, limiting the capacity expansion
Solution Approach 1:
The patent divides the storage medium into multiple wafers, each containing multiple dies with banks. This segmentation allows the total quantity of banks to be increased by adding more wafers rather than increasing the I/O circuit size on a single die. Each wafer acts as an independent module that can be added to expand capacity without proportionally increasing the complexity of individual I/O circuits.
Solution Approach 2:
The patent transitions from a single-die planar arrangement to a multi-wafer three-dimensional stacking architecture. By organizing storage medium wafers and controller wafers in vertical stacks, the system expands capacity in the vertical dimension rather than being constrained by the horizontal area available on a single die, thereby decoupling bank quantity from I/O circuit size.
2Quantity of substance
If the I/O circuit is connected to external memory controller through a bus, then the storage can be accessed externally, but the bit width of the memory is limited by the bus and cannot be expanded
Solution Approach 1:
The patent segments the data transmission path into multiple parallel channels by using multiple wafers with multiple banks each. Instead of a single bus connecting to a single I/O circuit, the system has multiple I/O circuits on different wafers that can transmit data simultaneously through separate pathways, effectively increasing bit width without requiring a single wider bus.
Solution Approach 2:
The patent merges multiple data transmission pathways by stacking multiple wafers with I/O circuits that can operate concurrently. The controller wafer coordinates multiple storage medium wafers, combining their data output capabilities to achieve high bit width. This merging of multiple channels provides both capacity expansion and bit width increase simultaneously.
3Quantity of substance
If multiple wafers are stacked to increase capacity, then the storage capacity can be greatly increased, but the control complexity and data access efficiency may be affected
Solution Approach 1:
The patent segments the controller into a controller wafer that coordinates multiple storage medium wafers. This segmentation allows the controller to manage capacity expansion systematically by treating each wafer as a manageable module, reducing the complexity burden compared to a monolithic controller trying to manage all banks simultaneously.
Solution Approach 2:
The controller wafer acts as an intermediary between external systems and the stacked storage medium wafers. It receives data access instructions, determines which storage medium wafers need to respond, and coordinates their operations. This intermediary layer simplifies the control architecture by providing a single entry point for managing multiple wafers.
Data Source
AI summary
A storage includes a first wafer and a second wafer that are stacked. The first wafer is a storage medium wafer, and a medium controller is disposed on the second wafer. The storage medium wafer includes a plurality of regions, each region includes a plurality of dies, and each die includes a plurality of banks. The medium controller is connected to each bank, and the medium controller can receive a data access instruction and access the bank based on the data access instruction. The medium controller can directly control the bank, and can perform operations concurrently on the plurality of banks, so that an amount of data transmitted between the storage medium wafer and the medium controller in a transmission periodicity can be increased, and a bit width of the storage is increased.