Stacked Semiconductor Wafer Bonding via Conductive Adhesive
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Solution Overview
Problem
The increasing demand for high-density, reduced-size, and low-cost memory devices poses challenges as existing technologies are labor-intensive and costly, and simply scaling chip size is impractical, necessitating alternative techniques that can utilize older memory chip technology without redesigning computer platforms.
Innovation Solution
A method of stacking semiconductor wafers by forming conductive adhesive layers between bondpad layers on each wafer, allowing for the bonding of multiple wafers to create a high-density memory structure, with each wafer containing device structure layers, metal connection layers, and passivation layers, enabling efficient electrical connections and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If new technologies with finer design rules are adopted to increase memory density, then memory capacity increases, but manufacturing cost and complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory expansion to three-dimensional vertical stacking. Multiple semiconductor wafers are stacked vertically and bonded together, utilizing the vertical dimension to increase memory capacity without requiring finer design rules or more complex manufacturing processes at the same technology node.
Solution Approach 2:
The patent implements a nested structure where multiple complete wafer assemblies (each containing device layers, metal layers, and passivation layers) are stacked and bonded together. Each wafer acts as a nested unit containing functional memory devices, with intermediate bondpad layers providing electrical connections between stacked wafers.
2Quantity of substance
If chip size is multiplied to increase memory density, then memory capacity increases, but device size increases
Solution Approach 1:
Instead of increasing memory capacity by expanding the horizontal area of single chips, the patent stacks multiple wafers vertically. This vertical integration allows memory capacity to scale in the third dimension while maintaining a compact footprint, effectively decoupling capacity from planar area.
3Quantity of substance
If multiple wafers are stacked to increase memory density, then memory capacity increases, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming bondpad layers and conductive adhesive layers on each wafer before stacking. This pre-preparation of bonding interfaces simplifies the overall stacking process, as each wafer is independently prepared with all necessary electrical connection structures before being assembled into the final stacked configuration.
Data Source
AI summary
A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer.