Stacked Wafer Bonding Pads for Warp-Tolerant NAND Assembly
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Solution Overview
Problem
The challenge of ensuring stable bonding between stacked semiconductor chips in three-dimensional NAND flash memory devices, particularly due to warping of array wafers, leading to insufficient contact area and potential defects at the bonding surface.
Innovation Solution
The dimensions of the metal pads on the stacked semiconductor chips are designed to satisfy specific ratios, such as PX1>PY1 or PY2>PX2, to secure a stable bonding surface even when positional deviations occur due to wafer warping, enhancing the integrity of the bond.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If array wafers are stacked to form three-dimensional NAND flash memory, then storage capacity is improved, but warping of array wafers causes insufficient contact area at bonding surfaces
Solution Approach 1:
The invention applies asymmetry by making the pad structure non-square, with different dimensions in the first direction (length) versus the second direction (width). Specifically, the pad has a first dimension PX and a second dimension PY where PX ≠ PY, creating an asymmetric geometry that compensates for warping-induced misalignment during stacking.
Solution Approach 2:
The invention applies local quality by creating different pad structures at different locations. Pads at different positions in the stacked configuration have different dimensional ratios (PX1/PY1, PX2/PY2, etc.) tailored to compensate for local warping variations. Each pad's asymmetric dimensions are specifically designed for its position in the stack to ensure adequate contact area despite warping.
2Reliability
If pad dimensions are increased to compensate for warping, then bonding reliability is improved, but device area and complexity increase
Solution Approach 1:
The invention applies parameter changes by systematically varying the dimensional parameters (PX, PY) of pads at different positions in the stack. The ratio PX/PY is adjusted as a key parameter to compensate for cumulative warping effects. This allows bonding reliability to be maintained through parameter optimization rather than increasing overall device complexity.
Data Source
AI summary
A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.PX1>PY1 (1)PY2>PX2 (2).