Stacked Wafer Dicing Layout for Higher Memory Chip Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor dicing process faces challenges in efficiently separating peripheral circuit chips and memory array chips, leading to reduced chip yield and throughput due to cleavage planes passing through the interiors of the chips, which affects the integration level and performance of two-dimensional memory devices.
Innovation Solution
A semiconductor structure is designed with specific markings and dicing lanes on wafers, where the cleavage plane is parallel to the dicing lane, allowing for precise dicing and reducing the likelihood of chips cleaving along their interiors, and a method involving stacking and simultaneous two-side dicing is employed to improve dicing efficiency and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional dicing process is used to separate peripheral circuit chips and memory array chips, then chips can be separated, but cleavage planes pass through the interiors of the chips causing reduced chip yield
Solution Approach 1:
The patent introduces a vertical stacking dimension to separate peripheral circuit chips and memory array chips into different spatial layers. By forming memory holes through the peripheral circuit chip substrate and inserting memory array chips vertically, the dicing planes for each chip type can be positioned at different depths, preventing cleavage planes from passing through chip interiors and thereby improving both dicing precision and chip yield.
Solution Approach 2:
The patent segments the semiconductor structure into distinct functional layers: peripheral circuit chips form the base layer while memory array chips are inserted into memory holes in separate vertical segments. This segmentation allows independent dicing operations on each layer with optimized dicing lanes, enabling precise separation without compromising chip integrity and improving overall manufacturing precision.
2Productivity
If dicing is performed to separate chips on a wafer, then individual chips can be obtained, but the process is time-consuming and reduces throughput
Solution Approach 1:
The patent merges multiple dicing operations into a single integrated process by designing dicing lanes that simultaneously separate both peripheral circuit chips and memory array chips. The through-type dicing lanes extend through the entire stacked structure, allowing one dicing action to accomplish separation of multiple chip types, thereby reducing total dicing time and improving throughput.
Solution Approach 2:
The patent implements continuous dicing lanes that extend through the entire thickness of the stacked semiconductor structure. This continuous dicing path allows the dicing blade to separate multiple layers of chips in one uninterrupted motion, eliminating the need for multiple separate dicing steps and significantly reducing the overall dicing time while maintaining high throughput.
Data Source
AI summary
According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.