Stacked Semiconductor Wafer Edge Support for Void-Free Bonding
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Solution Overview
Problem
In typical wafer bonding processes, gaps or voids can form at the edge portions of stacked semiconductor devices due to the thin thickness of the wafer bevel region, leading to potential delamination, cracking, or peeling during subsequent processes like wafer thinning.
Innovation Solution
A stacked semiconductor device is designed with insulation support patterns that are extended from the upper surface of the insulation layer to the wafer, and these patterns are bonded together during the wafer bonding process to provide enhanced supporting strength at the edge portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer bonding is performed with a thin wafer bevel region, then the bonding process can be completed, but gaps or voids are generated at the edge portions of the stacked semiconductor devices
Solution Approach 1:
The bevel region is formed in advance before wafer bonding to prepare the edge portions for proper alignment and contact. This preliminary structural preparation ensures that when bonding occurs, the edge portions are positioned correctly to minimize gap formation, directly addressing the precision issue while maintaining bonding productivity
Solution Approach 2:
The bevel region is applied locally at the edge portions of the wafers rather than uniformly across the entire wafer surface. This localized structural modification provides enhanced support and alignment at the critical edge areas where gaps typically form, without affecting the overall bonding process efficiency
2Productivity
If wafer bonding is performed with a thin wafer bevel region, then the bonding process can be completed, but delamination, cracking, or peeling occurs in subsequent wafer thinning processes
Solution Approach 1:
The bevel region is created in advance before bonding and subsequent thinning processes. This pre-formed structural feature provides ongoing support to the edge portions throughout the manufacturing sequence, preventing delamination and cracking during wafer thinning while allowing the bonding process to complete successfully
Solution Approach 2:
The bevel region acts as a protective cushion or support structure at the edge portions before the damaging thinning process occurs. This preliminary protective feature absorbs or distributes stresses that would otherwise cause delamination or cracking during subsequent CMP or other thinning operations
3Strength
If the wafer bevel region thickness is increased to prevent gap formation, then edge supporting strength is improved, but the wafer bonding process becomes more complex
Solution Approach 1:
Instead of uniformly increasing wafer thickness throughout, the bevel region provides localized thickness enhancement only at the edge portions where support is needed. This targeted approach improves edge supporting strength without requiring complex overall wafer design modifications or complicating the bonding process
Solution Approach 2:
The bevel region applies a partial thickness increase only where needed at the edges rather than excessive thickening across the entire wafer. This partial action provides sufficient edge support strength while maintaining simplicity in the bonding process by avoiding unnecessary material addition or structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of insulation support patterns effectively prevents delamination, cracking, or peeling at the edge portions of the stacked semiconductor device, even during processes like chemical mechanical polishing (CMP) for wafer thinning.
Implementation Method 1
Wafer bonding is a well-known technology for three-dimensionally stacking semiconductor devices with an integrated circuit (IC). Wafer bonding electrically connects at least two stacked semiconductor devices with each other.
Implementation Method 2
a delamination, a crack, a peeling, etc., at the edge portion of the stacked semiconductor device may be prevented in a following process such as a wafer thinning process using a chemical mechanical polishing (CMP) process
Data Source
AI summary
A stacked semiconductor device may include a first wafer and at least one first insulation support pattern. The first wafer may include a first surface having at least one insulation layer and a second surface opposite to the first surface. The first insulation support pattern may be extended from the first surface of the first wafer into the insulation layer. The first insulation support pattern may be formed in a region of the first surface where an integrated circuit may not be formed.