Stacked Wafer Global Shutter Pixels Using Capacitive Deep Trench Isolation
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Solution Overview
Problem
The challenge is to design image sensors with larger pixels of sufficient count for higher resolution while maintaining a compact size, as smaller pixels result in reduced charge storage capacity and worse signal-to-noise ratio, and rolling blade shutter pixels are inadequate for capturing fast-moving objects.
Innovation Solution
The solution involves splitting the pixel circuitry into sensing and storage portions on separate integrated circuit dies, with capacitive deep trench isolation used for storage capacitors, allowing for improved signal-to-noise ratio and compact design without the drawbacks of conventional ten transistor pixel designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pixel size is increased to improve charge storage capacity and signal-to-noise ratio, then image quality improves, but sensor area increases reducing compactness
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture, placing the photodetector array on one substrate and the storage capacitor array on another substrate vertically connected via through-silicon vias. This vertical stacking enables larger pixel area for improved charge storage capacity and signal-to-noise ratio while maintaining a compact footprint by utilizing the third dimension (height) rather than expanding the sensor plane area.
2Productivity
If more pixels are packed into a given area to increase resolution, then pixel count increases, but individual pixel size decreases reducing charge storage capacity
Solution Approach 1:
By stacking the storage capacitor array vertically beneath the photodetector array and connecting them through through-silicon vias, the patent enables each pixel to access a larger total area for charge storage without increasing the lateral pixel pitch. This vertical expansion of the pixel footprint allows higher pixel counts per unit area while maintaining sufficient charge storage capacity in each pixel.
3Area of stationary object
If rolling blade shutter is used to reduce pixel area, then sensor compactness improves, but capability to capture fast-moving objects deteriorates
Solution Approach 1:
The patent divides the pixel circuitry into two separate functional arrays on different substrates: a photodetector array for light sensing and a storage capacitor array for charge storage. This segmentation allows the photodetector area to be minimized for compactness while the storage capacitors are placed vertically beneath, providing sufficient charge storage capacity. The separated architecture reduces parasitic light sensitivity and enables global shutter operation for capturing fast-moving objects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the signal-to-noise ratio and allows for higher resolution while maintaining a compact sensor size, enabling better image quality and reduced parasitic light sensitivity, suitable for both global and rolling shutter applications.
Implementation Method 1
The at least one storage capacitor is formed from a capacitive deep trench isolation
Data Source
AI summary
Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least one photodiode to a read voltage and to selectively output the read voltage. A second integrated circuit die is in a stacked arrangement with the first integrated circuit die and has formed therein storage circuitry to selectively transfer the read voltage to at least one storage capacitor for storage as a stored voltage and to selectively transfer the stored voltage to an output. The at least one storage capacitor is formed from a capacitive deep trench isolation. There is an interconnect between the first and second integrated circuit dies for coupling the readout circuitry to the storage circuitry.