Stacked Wafer Dicing with Intermediate Layer Removal

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Solution Overview

Problem

Stealth dicing of stacked wafers in semiconductor manufacturing can cause peeling at bonding interfaces due to laser thermal impact and stress from linear expansion differences between layers, particularly in thin substrates like those used in liquid ejection heads.

Innovation Solution

The method involves dicing stacked wafers by forming modified regions with laser beams and removing specific layers along the cutting lines, including intermediate layers such as insulating and adhesion improvement layers, to mitigate thermal stress and reduce peeling at bonding interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If laser beam irradiation is performed for stealth dicing of stacked wafers, then dicing accuracy is improved, but peeling at bonding interfaces occurs due to thermal impact and stress

Engineering Contradiction:
Improvedicing accuracyVSAvoidbonding interface integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent removes the intermediate layer along the cutting line before performing laser irradiation. This preliminary removal prevents the intermediate layer from being exposed to laser thermal impact, thereby avoiding stress-induced peeling at the bonding interface while still enabling precise stealth dicing of the stacked wafers

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the intermediate layer (insulating layer or adhesion improvement layer) from the bonding interface region along the cutting line. By removing this specific layer that causes thermal stress, the bonding interface is protected from laser-induced peeling while maintaining the integrity of the stacked wafer structure

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If intermediate layers are removed along cutting lines to prevent peeling, then bonding interface reliability is improved, but process complexity increases

Engineering Contradiction:
Improvebonding interface integrityVSAvoiddicing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the intermediate layer removal step with the existing stealth dicing process flow. By integrating these operations and utilizing existing laser processing capabilities, the additional complexity is minimized while achieving improved bonding interface reliability

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces wafer peeling at bonding interfaces by minimizing stress from linear expansion differences, ensuring precise and reliable separation of stacked semiconductor chips.

Implementation Method 1

laser beams are emitted and focused at a predetermined depth along a predetermined dicing line, forming a modified region with low crystal strength

Methodology Applied
Scientific EffectLaser thermal impact: Laser

Implementation Method 2

stress due to the difference in liner expansion of a plurality of layers on the bonding interface

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250312871A1Method for manufacturing semiconductor chip and method for dicing stacked wafer
Publication Date: 2025.10.09 CANON KK
  • US20250312871A1 patent drawing
  • US20250312871A1 patent drawing
  • US20250312871A1 patent drawing

AI summary

A method for manufacturing a plurality of semiconductor chips from a stacked wafer in which a first wafer and a second wafer are joined with adhesive, and at least one of the first wafer and the second wafer includes an intermediate layer provided on a side joined to the adhesive. The method comprises dicing the stacked wafer along a cutting line with cracks generated in a modified region formed by irradiation of laser beam from the first wafer. The dicing includes irradiating laser beam along a region where the first wafer is removed along the cutting line with a laser beam.