Stacked Wafer Level Package Module Bottom Pad Design
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Solution Overview
Problem
Conventional wafer level packages face difficulties in stacking due to solder balls attached to redistribution layers on the side surfaces of semiconductor chips, making it challenging to create multi-layered semiconductor package modules effectively.
Innovation Solution
A stacked wafer level package module design where rectangular semiconductor chips are aligned with exposed pads and connection members, such as solder layers and balls, to facilitate stacking and connection over a substrate, with an adhesive member and insulation layers for stability and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder balls are attached to redistribution layers on side surfaces of semiconductor chips, then conventional wafer level packages can be manufactured, but stacking of wafer level packages becomes difficult
Solution Approach 1:
The patent transitions from side-surface mounting (2D plane) to bottom-surface mounting (changing the dimension of attachment). By placing pads and solder balls on the bottom surface of the semiconductor chip instead of on side surfaces, the chip can be stacked vertically on substrates, enabling multi-layer packaging configurations that were not possible with conventional side-surface attachment methods.
2Productivity
If multiple semiconductor packages are stacked to increase data storage capacity and processing speed, then functionality is enhanced, but structural integrity and volume control become challenging
Solution Approach 1:
The patent divides the semiconductor package into distinct functional layers: substrate, semiconductor chip, and encapsulant, each with specific attachment surfaces optimized for their function. The bottom surface of the chip is segmented to include both pads for electrical connection and areas for mechanical attachment, allowing multiple chips to be stacked while maintaining structural integrity through proper distribution of connection points.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically on substrates, with each chip containing encapsulated semiconductor devices. The encapsulant nests within the chip structure, and multiple chip-substrate assemblies can be nested together to form multi-layer packages, maximizing space utilization while maintaining structural coherence.
3Device complexity
If pads are exposed on the lower surface of semiconductor chips for stacking, then multi-layered packages can be formed, but pad protection and insulation become more difficult
Solution Approach 1:
The patent applies different properties to different regions of the chip bottom surface. Pads are provided with conductive material for electrical connection, while surrounding areas are covered with insulating materials or left as bonding pads for mechanical attachment. This local differentiation allows pads to be exposed and accessible for stacking while maintaining proper electrical insulation and mechanical protection where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient stacking and connection of multiple semiconductor chips, enhancing data storage capacity and processing speed by allowing for multi-layered packages without compromising structural integrity or increasing volume significantly.
Implementation Method 1
an adhesive member interposed between the first and second rectangular shaped semiconductor chips fixing the first rectangular shaped semiconductor chip to the second rectangular shaped semiconductor chip
Implementation Method 2
a first connection member connecting the first pad to the first connection pad; and a second connection member connecting the second pad to the second connection pad
Data Source
AI summary
A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.