3D Memory Device with Stacked Wafers and Dynamic Block Allocation
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Solution Overview
Problem
Current memory devices face inefficiencies in data storage and performance due to the limitations of traditional three-dimensional nonvolatile memory devices, particularly in managing and optimizing the use of memory blocks in a way that maximizes storage capacity and access speed.
Innovation Solution
The implementation of a memory device structure that includes a small block on one wafer and a large block on another wafer stacked vertically, with a memory controller that dynamically allocates storage based on data size, allowing for efficient data write operations by selecting between small and large blocks depending on the size of the write-requested data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional three-dimensional nonvolatile memory device with uniform memory blocks is used, then the storage capacity is increased, but the write efficiency and performance deteriorate due to inability to optimize for different data sizes
Solution Approach 1:
The memory device is divided into multiple memory blocks with different sizes (first memory blocks and second memory blocks) on different wafers. This segmentation allows the system to select appropriate block sizes based on data size, improving write efficiency by matching storage structure to data characteristics rather than using uniform blocks for all scenarios.
2Area of stationary object
If memory blocks are stacked vertically to increase integration, then the storage capacity per area is improved, but the complexity of wiring and interconnections increases
Solution Approach 1:
Multiple memory blocks are stacked vertically in the third dimension rather than being arranged horizontally in the same plane. This vertical stacking increases storage capacity per area while the patent manages wiring complexity through systematic interconnection design between corresponding blocks on different wafers.
3Ease of manufacture
If a single wafer with uniform memory blocks is used, then the manufacturing process is simplified, but the memory utilization efficiency deteriorates due to inability to dynamically allocate storage based on data size
Solution Approach 1:
Different memory blocks on different wafers are designed with different sizes tailored to specific data size requirements. This local differentiation in block size allows optimal matching between storage structure and data characteristics, improving memory utilization efficiency while maintaining systematic manufacturing processes.
4Quantity of substance
If memory blocks are stacked vertically across multiple wafers, then the storage capacity and performance are improved, but the difficulty of detecting and measuring block characteristics increases
Solution Approach 1:
The patent introduces a control logic component that acts as an intermediary between the external interface and the vertically stacked memory blocks. This control logic receives data size information, determines the appropriate block size, and directs write operations to the correct memory blocks, simplifying the detection and measurement process by centralizing the decision-making function.
Data Source
AI summary
A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.