Stacked Wafer Level Package Using Chip Substrate for Reduced Size
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Solution Overview
Problem
The existing stacked semiconductor packages require conductive wires or through-electrodes for electrical connections, leading to increased size, complexity, and defective manufacturing rates due to the need for via holes in the semiconductor chips.
Innovation Solution
A stacked wafer level package design that eliminates the use of conductive wires and through-electrodes by stacking semiconductor chips with redistribution structures and adhesive members, where one semiconductor chip acts as a substrate for the others, reducing volume, thickness, and weight, and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive wires are used to electrically connect semiconductor chips in a stacked package, then electrical connection between chips is achieved, but the size of the package is increased greatly
Solution Approach 1:
The patent removes conductive wires from the stacked package structure, eliminating the need for separate connection elements between chips. The chips are directly bonded to each other through their bonding pads, extracting the unnecessary wire bonding component from the system.
Solution Approach 2:
The patent merges the electrical connection function directly into the chip bonding interface. The bonding pads on adjacent chips establish electrical connection simultaneously with the mechanical bonding, combining structural support and electrical connectivity into a single integrated interface without separate wire bonds.
2Reliability
If through electrodes are used to electrically connect semiconductor chips in a stacked package, then electrical connection between chips is achieved, but the fabrication process becomes more complicated and defective manufacturing rate is greatly increased
Solution Approach 1:
The patent extracts through electrodes from the chip structure, eliminating the need to form via holes through the semiconductor chips. This removes the complex fabrication steps associated with creating and filling through-electrode vias while maintaining electrical connectivity through direct bonding pad contact.
Solution Approach 2:
Instead of creating through-electrodes that penetrate the chip substrate, the patent inverts the approach by establishing electrical connections at the chip surfaces through bonding pads that contact directly with adjacent chips, reversing the conventional through-electrode methodology.
3Reliability
If via holes are formed in semiconductor chips to create through electrodes, then electrical connection is achieved, but defective manufacturing rate is greatly increased
Solution Approach 1:
The patent removes the via hole formation process entirely from the manufacturing sequence. By eliminating through-electrode requirements, the method avoids defects associated with via drilling, plating, and filling operations, thereby reducing overall manufacturing defect rates.
Solution Approach 2:
The patent inverts the conventional approach by making electrical connections at the chip surfaces rather than through the chip substrates. This reversal eliminates the high-defect via hole formation process while maintaining effective electrical connectivity between stacked chips.
Data Source
AI summary
A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.