Stacked Multi-Chip Wafer Package for Stable Voltage and Fewer Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of multi-chip wafer level packages while maintaining integration density and preventing voltage fluctuations due to the complexity of packaging smaller components and the need for efficient decoupling capacitors.
Innovation Solution
A multi-chip wafer level package structure is developed, featuring a first tier with a redistribution layer and integrated passive devices, and a second tier with active devices, where decoupling capacitors are strategically placed to stabilize voltage and reduce the number of through integrated fan-out vias, allowing for increased pitch and broader process windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the physical size of the package is reduced, then the area occupied by the package decreases, but the integration density and voltage stability become difficult to maintain
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture with multiple tiers. Active devices are placed on a first tier while decoupling capacitors are positioned on a second tier above them, enabling vertical integration. This dimensional change allows the package to maintain compact footprint while accommodating both signal processing and power stabilization functions within the same area, thus reducing package area without compromising voltage stability.
Solution Approach 2:
The patent implements a nested structure where the second tier containing decoupling capacitors is positioned directly above the first tier containing active devices. The capacitors are vertically aligned and coupled to the active devices through through-integrated fan-out vias, creating a compact nested arrangement. This nesting allows the decoupling function to be integrated within the same lateral footprint as the active devices, reducing overall package area while maintaining voltage stability through close proximity coupling.
2Reliability
If decoupling capacitors are placed close to active devices, then voltage stability improves, but the number of through integrated fan-out vias increases
Solution Approach 1:
The patent resolves the via complexity issue by moving the decoupling capacitors to a second tier above the active devices on the first tier. This vertical stacking eliminates the need for numerous lateral via connections that would be required in a planar layout. The through-integrated fan-out vias are used only for essential inter-tier connections, significantly reducing the total via count while maintaining close coupling between capacitors and active devices for voltage stability.
Solution Approach 2:
The patent introduces an intermediate substrate structure that provides integrated fan-out vias as a mediator between the first tier active devices and the second tier decoupling capacitors. This intermediary substrate enables efficient vertical electrical connections while managing the via complexity by consolidating connection paths and providing a structured routing layer that simplifies the interconnection architecture.
3Quantity of substance
If more components are integrated into a given area, then integration density increases, but the minimum feature size must be reduced
Solution Approach 1:
The patent achieves high integration density without reducing minimum feature size by exploiting the third dimension. Multiple tiers are stacked vertically with active devices on the first tier and decoupling capacitors on the second tier. This vertical integration allows more functional components to be packed into the same lateral footprint while maintaining larger, more manufacturable feature sizes on each individual tier, thus improving integration density without compromising manufacturing precision.
Data Source
AI summary
Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.