Stacked Wafer Bonding Pad Layout for Lower Contact Resistance
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Solution Overview
Problem
The complexity of manufacturing semiconductor package structures increases due to the integration of various materials with different thermal properties, necessitating improved manufacturing processes to address challenges such as bonding pad dishing and contact resistance.
Innovation Solution
A semiconductor package structure is developed with multiple bonding pads on each wafer, where the second and third bonding pads on the second wafer are bonded to the first bonding pad on the first wafer, and a via is formed to penetrate through the second wafer, reducing bonding pad dishing and increasing contact areas for enhanced performance by providing reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bonding pads are integrated on each wafer to increase memory capacity and mounting density, then productivity and functionality are improved, but device complexity and manufacturing difficulty increase due to various materials with different thermal properties
Solution Approach 1:
The bonding pad structure is segmented into multiple pads (first bonding pad, second bonding pad, third bonding pad) distributed across different wafers, allowing independent bonding operations and reducing the complexity of bonding large-area pads while achieving high memory capacity through stacked configuration
Solution Approach 2:
Multiple wafers are stacked in a nested configuration where the first wafer, second wafer, and third wafer are vertically arranged with bonding pads from different wafers bonded together, creating a three-dimensional integrated structure that increases memory capacity without increasing footprint area
2Manufacturing precision
If planarization process is applied to bonding pads to achieve flat surface, then manufacturing precision is improved, but bonding pad dishing occurs causing contact resistance issues
Solution Approach 1:
The via structure is designed with local quality variations - the via extends through the second wafer and makes contact with the first bonding pad at a specific depth, allowing the bonding pad surface to be planarized for manufacturing precision while the via maintains reliable electrical contact by reaching the appropriate bonding pad region
Solution Approach 2:
The via acts as an intermediary element that bridges the second bonding pad/third bonding pad region and the first bonding pad, enabling electrical connection while accommodating the planarized surface topology and reducing the impact of bonding pad dishing on contact resistance
3Reliability
If via is formed to penetrate through second wafer to contact first bonding pad, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The via is formed through the second wafer before final bonding operations, and the second bonding pad and third bonding pad are subsequently bonded to the first bonding pad through this pre-formed via, allowing contact resistance to be minimized while organizing manufacturing operations in a logical sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces bonding pad dishing during planarization and enhances the semiconductor package structure's performance by increasing contact areas and reducing contact resistance, thereby improving the manufacturing efficiency and functionality of the semiconductor package.
Implementation Method 1
bonding the second semiconductor wafer onto the first semiconductor wafer using a hybrid bonding process such that the second bonding pad and the third bonding pad are bonded to the first bonding pad
Data Source
AI summary
A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.