Stacked Wafer Level Package With Exposed Redistribution Patterns
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Solution Overview
Problem
Existing semiconductor packages face challenges in stacking multiple wafer level packages due to the redistribution pattern on the surface and solder balls attached to them, limiting data storage capacity and processing speed.
Innovation Solution
A semiconductor package structure is developed with a base substrate, semiconductor chips, insulation layers, and redistribution patterns that allow for the stacking of multiple wafer level packages by exposing specific portions of the redistribution patterns, enabling enhanced data storage and processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a redistribution pattern is disposed on the surface of the wafer level package with solder balls attached, then electrical connection and signal transmission are achieved, but stacking of multiple wafer level packages becomes impossible
Solution Approach 1:
The package surface is segmented into different functional regions: a chip region with solder balls for electrical connection and a peripheral region with exposed redistribution patterns for stacking. This segmentation allows the package to simultaneously achieve electrical connectivity and stacking capability by dedicating different areas to different functions.
Solution Approach 2:
The invention transitions from two-dimensional surface mounting to three-dimensional stacking by utilizing the peripheral region for vertical interconnection. The exposed redistribution patterns in the peripheral region enable packages to be stacked vertically, adding a third dimension to the package architecture and dramatically increasing data processing capacity.
2Reliability
If solder balls are attached to the redistribution pattern for electrical connection, then signal transmission is achieved, but the surface area available for stacking is reduced
Solution Approach 1:
Different regions of the package surface are assigned different properties: the chip region has solder balls attached for reliable electrical connection, while the peripheral region has exposed redistribution patterns without solder balls for stacking. This local differentiation allows each region to optimize its function without compromising the other.
Solution Approach 2:
The solder balls are extracted from the peripheral region and retained only in the chip region. This extraction allows the peripheral redistribution patterns to remain exposed and accessible for stacking operations, while the chip region maintains its electrical connection functionality through solder ball attachment.
3Object-affected harmful factors
If the entire redistribution pattern is covered for protection, then the semiconductor chip is protected from external impact, but stacking of multiple packages becomes impossible
Solution Approach 1:
The insulation layer coverage is applied locally rather than uniformly: it covers the chip region to protect the semiconductor chip from external impact, while leaving the peripheral region exposed to enable stacking. This selective coverage strategy simultaneously achieves protection and stacking capability.
Solution Approach 2:
The package surface is segmented into a protected chip region and an exposed peripheral region. The insulation layer is applied to the chip region for protection, while the peripheral region remains accessible for stacking operations, allowing the package to simultaneously achieve impact resistance and stacking functionality.
Data Source
AI summary
A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.