Stacked Wafer Slice Packaging for Low-Distortion RF Devices

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Solution Overview

Problem

Conventional silicon substrates used in microelectronics packages, particularly for RF devices, suffer from harmonic distortion and low resistivity, limiting their performance and compatibility with low-profile requirements of portable electronic devices.

Innovation Solution

A microelectronics package with a vertically stacked structure of two or more wafer slices, where each wafer slice includes a device region, passivation layers, and connecting layers to facilitate electrical connections, and a mold compound with high thermal conductivity and low dielectric constant, to reduce harmonic distortion and enhance performance while meeting low-profile requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional silicon substrates are used for RF devices, then low cost and large scale production are achieved, but harmonic distortion and low resistivity occur

Engineering Contradiction:

Improvelow cost and large scale productionVSAvoidharmonic distortion and resistivity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the substrate into a stacked structure of multiple wafer slices (first wafer slice, second wafer slice, third wafer slice) bonded together. Each wafer slice can be independently fabricated using conventional silicon processes, maintaining manufacturing ease, while the stacked configuration eliminates harmonic distortion by removing continuous silicon crystal between device regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a composite substrate structure by bonding multiple wafer slices together with bonding layers in between. This composite structure combines the advantages of conventional silicon fabrication with the performance benefits of disrupted silicon continuity, achieving both low cost and improved RF performance without harmonic distortion.

Inventive Principle:

Principle #40Composite materials

2Area of moving object

If vertically stacked semiconductor devices are used to achieve electronics densification, then small footprint is achieved, but large package thickness occurs

Engineering Contradiction:

ImprovefootprintVSAvoidpackage thickness

Core Design Contradiction:

Area of moving objectVSLength of stationary object

Solution Approach 1:

The patent redistributes the vertical thickness across multiple horizontally stacked wafer slices rather than stacking devices vertically within a single thick substrate. This dimensional redistribution maintains small footprint while reducing the thickness of each individual wafer slice, enabling low-profile packaging.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the thick substrate into multiple thin wafer slices bonded together. Each wafer slice has reduced thickness compared to a single stacked device structure, and the bonding layers provide mechanical support while maintaining electrical isolation, achieving both densification and low profile.

Inventive Principle:

Principle #1Segmentation

3Reliability

If multiple wafer slices are stacked vertically, then harmonic distortion is reduced and performance is enhanced, but device complexity increases

Engineering Contradiction:

Improveharmonic distortion reductionVSAvoidstacked wafer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the structural parameter of the substrate from a single continuous silicon crystal to multiple bonded wafer slices with bonding layers. This parameter change disrupts the silicon continuity that causes harmonic distortion while maintaining compatibility with conventional silicon fabrication processes, avoiding the need for expensive or complex manufacturing.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces harmonic distortion and accommodates low-profile needs, enhancing the performance and thermal management of microelectronics packages, particularly for RF devices, without requiring expensive or complex processes.

Implementation Method 1

The top via is in contact with the first through-via, such that the second FEOL portion is electrically connected to the first FEOL portion

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

a mold compound with high thermal conductivity and low dielectric constant

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240030126A1Microelectronics package with vertically stacked wafer slices and process for making the same

Publication Date: 2024.01.25 QORVO US INC

AI summary

The present disclosure relates to a microelectronics package with a vertically stacked structure of two or more wafer slices. A first wafer slice includes a first device region and a through-via connected to the first device region through a first connecting layer. A second wafer slice, which is vertically stacked underneath the first wafer slice, includes a second device region and a top via connected to the second device region through a second connecting layer. The top via in the second wafer slice is in contact with the through-via in the first wafer slice, such that the first device region is electrically connected to the second first device region. Herein, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first device region and the second device region.